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| author | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2021-08-17 11:06:55 +0200 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2021-08-20 19:06:30 -0400 |
| commit | 5806c386eb640247f6aa8983132c6b193195ea4a (patch) | |
| tree | 08c05374dc59894c46f7578894a1f4c6af7d9489 /src | |
| parent | e48d7bbb99a81d9e6058aa764266dcc3dbe71644 (diff) | |
| download | zig-5806c386eb640247f6aa8983132c6b193195ea4a.tar.gz zig-5806c386eb640247f6aa8983132c6b193195ea4a.zip | |
stage2 codegen: re-allocate result register in finishAir
In some cases (such as bitcast), an operand may be the same MCValue as
the result. If that operand died and was a register, it was freed by
processDeath. We have to "re-allocate" the register.
Diffstat (limited to 'src')
| -rw-r--r-- | src/codegen.zig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/codegen.zig b/src/codegen.zig index dd7f1d55b7..ca7a04a4a0 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -973,6 +973,20 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { log.debug("%{d} => {}", .{ inst, result }); const branch = &self.branch_stack.items[self.branch_stack.items.len - 1]; branch.inst_table.putAssumeCapacityNoClobber(inst, result); + + switch (result) { + .register => |reg| { + // In some cases (such as bitcast), an operand + // may be the same MCValue as the result. If + // that operand died and was a register, it + // was freed by processDeath. We have to + // "re-allocate" the register. + if (self.register_manager.isRegFree(reg)) { + self.register_manager.getRegAssumeFree(reg, inst); + } + }, + else => {}, + } } self.finishAirBookkeeping(); } |
