Merge branch 'master' into comment-in-array

1 files changed, 57 insertions, 0 deletions

diff --git a/src/zig_llvm.cpp b/src/zig_llvm.cpp
index fe1b279cf0..c51c9e1a50 100644
--- a/src/zig_llvm.cpp
+++ b/src/zig_llvm.cpp
@@ -39,7 +39,9 @@
 #include <llvm/Support/TargetParser.h>
 #include <llvm/Support/Timer.h>
 #include <llvm/Support/raw_ostream.h>
+#include <llvm/Support/TargetRegistry.h>
 #include <llvm/Target/TargetMachine.h>
+#include <llvm/Target/CodeGenCWrappers.h>
 #include <llvm/Transforms/Coroutines.h>
 #include <llvm/Transforms/IPO.h>
 #include <llvm/Transforms/IPO/AlwaysInliner.h>
@@ -93,6 +95,61 @@ static const bool assertions_on = true;
 static const bool assertions_on = false;
 #endif
 
+LLVMTargetMachineRef ZigLLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple,
+    const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc,
+    LLVMCodeModel CodeModel, bool function_sections)
+{
+    Optional<Reloc::Model> RM;
+    switch (Reloc){
+        case LLVMRelocStatic:
+            RM = Reloc::Static;
+            break;
+        case LLVMRelocPIC:
+            RM = Reloc::PIC_;
+            break;
+        case LLVMRelocDynamicNoPic:
+            RM = Reloc::DynamicNoPIC;
+            break;
+        case LLVMRelocROPI:
+            RM = Reloc::ROPI;
+            break;
+        case LLVMRelocRWPI:
+            RM = Reloc::RWPI;
+            break;
+        case LLVMRelocROPI_RWPI:
+            RM = Reloc::ROPI_RWPI;
+            break;
+        default:
+            break;
+    }
+
+    bool JIT;
+    Optional<CodeModel::Model> CM = unwrap(CodeModel, JIT);
+
+    CodeGenOpt::Level OL;
+    switch (Level) {
+        case LLVMCodeGenLevelNone:
+            OL = CodeGenOpt::None;
+            break;
+        case LLVMCodeGenLevelLess:
+            OL = CodeGenOpt::Less;
+            break;
+        case LLVMCodeGenLevelAggressive:
+            OL = CodeGenOpt::Aggressive;
+            break;
+        default:
+            OL = CodeGenOpt::Default;
+            break;
+    }
+
+    TargetOptions opt;
+    opt.FunctionSections = function_sections;
+
+    TargetMachine *TM = reinterpret_cast<Target*>(T)->createTargetMachine(Triple, CPU, Features, opt, RM, CM,
+            OL, JIT);
+    return reinterpret_cast<LLVMTargetMachineRef>(TM);
+}
+
 bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machine_ref, LLVMModuleRef module_ref,
         const char *filename, ZigLLVM_EmitOutputType output_type, char **error_message, bool is_debug,
         bool is_small, bool time_report)