Merge pull request #24302 from alexrp/riscv

Native RISC-V bootstrap and test fixes

1 files changed, 10 insertions, 6 deletions

diff --git a/src/zig_llvm.cpp b/src/zig_llvm.cpp
index cb624ea256..fe4e421dc3 100644
--- a/src/zig_llvm.cpp
+++ b/src/zig_llvm.cpp
@@ -260,6 +260,16 @@ ZIG_EXTERN_C bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machi
 
     TargetMachine &target_machine = *reinterpret_cast<TargetMachine*>(targ_machine_ref);
 
+    if (options->allow_fast_isel) {
+        target_machine.setO0WantsFastISel(true);
+    } else {
+        target_machine.setFastISel(false);
+    }
+
+    if (!options->allow_machine_outliner) {
+        target_machine.setMachineOutliner(false);
+    }
+
     Module &llvm_module = *unwrap(module_ref);
 
     // Pipeline configurations
@@ -385,12 +395,6 @@ ZIG_EXTERN_C bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machi
         }
     }
 
-    if (options->allow_fast_isel) {
-        target_machine.setO0WantsFastISel(true);
-    } else {
-        target_machine.setFastISel(false);
-    }
-
     // Optimization phase
     module_pm.run(llvm_module, module_am);