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| author | Andrew Kelley <andrew@ziglang.org> | 2020-01-26 09:57:25 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-26 09:57:25 -0500 |
| commit | 96e5f476c3f7f44d0b299bc6043f3fd88769bd8b (patch) | |
| tree | 5aadd86ef359eb847bf842f9594690737f0e67c4 /src/zig_llvm.cpp | |
| parent | 4e9b1f5479e3b7ce47d059e0e6f3d62cd4ee7254 (diff) | |
| parent | 3839ea89785856bbed0624a6a18eb6e5acfb46c3 (diff) | |
| download | zig-96e5f476c3f7f44d0b299bc6043f3fd88769bd8b.tar.gz zig-96e5f476c3f7f44d0b299bc6043f3fd88769bd8b.zip | |
Merge pull request #4264 from ziglang/layneson-cpus_and_features
Add support for target details (CPUs and their supported features)
Diffstat (limited to 'src/zig_llvm.cpp')
| -rw-r--r-- | src/zig_llvm.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/zig_llvm.cpp b/src/zig_llvm.cpp index b5c43b632b..614d31dc5a 100644 --- a/src/zig_llvm.cpp +++ b/src/zig_llvm.cpp @@ -821,7 +821,7 @@ const char *ZigLLVMGetSubArchTypeName(ZigLLVM_SubArchType sub_arch) { case ZigLLVM_ARMSubArch_v8_1a: return "v8.1a"; case ZigLLVM_ARMSubArch_v8: - return "v8"; + return "v8a"; case ZigLLVM_ARMSubArch_v8r: return "v8r"; case ZigLLVM_ARMSubArch_v8m_baseline: @@ -831,7 +831,7 @@ const char *ZigLLVMGetSubArchTypeName(ZigLLVM_SubArchType sub_arch) { case ZigLLVM_ARMSubArch_v8_1m_mainline: return "v8.1m.main"; case ZigLLVM_ARMSubArch_v7: - return "v7"; + return "v7a"; case ZigLLVM_ARMSubArch_v7em: return "v7em"; case ZigLLVM_ARMSubArch_v7m: |