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authorVeikka Tuominen <git@vexu.eu>2023-05-26 23:29:05 +0300
committerAndrew Kelley <andrew@ziglang.org>2023-05-26 21:42:19 -0700
commitca16f1e8a703491bcaac0d13379d2556e8ca837d (patch)
treefefadd0912e8e3deedbf0a7261219fbd7ee5149f /src/value.zig
parentdbd44658ff2d392451ea4f3a38ca4bd26da34314 (diff)
downloadzig-ca16f1e8a703491bcaac0d13379d2556e8ca837d.tar.gz
zig-ca16f1e8a703491bcaac0d13379d2556e8ca837d.zip
std.Target adjustments
* move `ptrBitWidth` from Arch to Target since it needs to know about the abi * double isn't always 8 bits * AVR uses 1-byte alignment for everything in GCC
Diffstat (limited to 'src/value.zig')
-rw-r--r--src/value.zig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/value.zig b/src/value.zig
index 93edf60eb2..613c3d9ca6 100644
--- a/src/value.zig
+++ b/src/value.zig
@@ -1922,7 +1922,7 @@ pub const Value = extern union {
.variable,
.eu_payload_ptr,
.opt_payload_ptr,
- => return target.cpu.arch.ptrBitWidth(),
+ => return target.ptrBitWidth(),
else => {
var buffer: BigIntSpace = undefined;