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| author | Andrew Kelley <andrew@ziglang.org> | 2021-09-20 16:48:42 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2021-09-20 16:48:42 -0700 |
| commit | abc30f79489b68f6dc0ee4b408c63a8e783215d1 (patch) | |
| tree | 0979982ebfa529405ae0e6014f910a3cf496aa14 /src/type.zig | |
| parent | 4b2d7a9c67760aa9a81bfd364ac0d88cbb9737f1 (diff) | |
| download | zig-abc30f79489b68f6dc0ee4b408c63a8e783215d1.tar.gz zig-abc30f79489b68f6dc0ee4b408c63a8e783215d1.zip | |
stage2: improve handling of 0 bit types
* Sema: zirAtomicLoad handles 0-bit types correctly
* LLVM backend: when lowering function types, elide parameters
with 0-bit types.
* Type: abiSize handles u0/i0 correctly
Diffstat (limited to 'src/type.zig')
| -rw-r--r-- | src/type.zig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/type.zig b/src/type.zig index 122faefbc7..c2dc150347 100644 --- a/src/type.zig +++ b/src/type.zig @@ -1822,6 +1822,7 @@ pub const Type = extern union { .int_signed, .int_unsigned => { const bits: u16 = self.cast(Payload.Bits).?.data; + if (bits == 0) return 0; return std.math.ceilPowerOfTwoPromote(u16, (bits + 7) / 8); }, |