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authorAndrew Kelley <andrew@ziglang.org>2021-03-28 23:12:26 -0700
committerAndrew Kelley <andrew@ziglang.org>2021-03-28 23:12:26 -0700
commit623d5f442c832ec0ea2a07aba73b8e2eae57191c (patch)
treebea996aaf34c60b2be183754415905ee1c77c2f4 /src/type.zig
parent281a7baaeac6b6b3c8c78124f5e484f7ee101cf0 (diff)
downloadzig-623d5f442c832ec0ea2a07aba73b8e2eae57191c.tar.gz
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stage2: guidance on how to implement switch expressions
Here's what I think the ZIR should be. AstGen is not yet implemented to match this, and the main implementation of analyzeSwitch in Sema is not yet implemented to match it either. Here are some example byte size reductions from master branch, with the ZIR memory layout from this commit: ``` switch (foo) { a => 1, b => 2, c => 3, d => 4, } ``` 184 bytes (master) => 40 bytes (this branch) ``` switch (foo) { a, b => 1, c..d, e, f => 2, g => 3, else => 4, } ``` 240 bytes (master) => 80 bytes (this branch)
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