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authorAlex Rønne Petersen <alex@alexrp.com>2025-02-15 02:44:58 +0100
committerAlex Rønne Petersen <alex@alexrp.com>2025-02-22 04:12:46 +0100
commitfc7a0c4878dac2d721ec18cafe1b6bcff7faa771 (patch)
tree5b9e4ef2d18e3daaf4bee34ae1bfe5af97916e8a /src/target.zig
parentd31bda13cb1ece7dd2ba22339172a8704a84823c (diff)
downloadzig-fc7a0c4878dac2d721ec18cafe1b6bcff7faa771.tar.gz
zig-fc7a0c4878dac2d721ec18cafe1b6bcff7faa771.zip
Sema: Fix fnptr alignment safety checks to account for potential ISA tag.
As seen on e.g. Arm/Thumb and MIPS (MIPS16/microMIPS). Fixes #22888.
Diffstat (limited to 'src/target.zig')
-rw-r--r--src/target.zig11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/target.zig b/src/target.zig
index 8ccec7f7a8..d032b0d16e 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -626,6 +626,17 @@ pub fn supportsFunctionAlignment(target: std.Target) bool {
};
}
+pub fn functionPointerMask(target: std.Target) ?u64 {
+ // 32-bit Arm uses the LSB to mean that the target function contains Thumb code.
+ // MIPS uses the LSB to mean that the target function contains MIPS16/microMIPS code.
+ return if (target.cpu.arch.isArm() or target.cpu.arch.isMIPS32())
+ ~@as(u32, 1)
+ else if (target.cpu.arch.isMIPS64())
+ ~@as(u64, 1)
+ else
+ null;
+}
+
pub fn supportsTailCall(target: std.Target, backend: std.builtin.CompilerBackend) bool {
switch (backend) {
.stage1, .stage2_llvm => return @import("codegen/llvm.zig").supportsTailCall(target),