stage2: start the InternPool transition

Instead of doing everything at once which is a hopelessly large task,
this introduces a piecemeal transition that can be done in small
increments at a time.

This is a minimal changeset that keeps the compiler compiling. It only
uses the InternPool for a small set of types.

Behavior tests are not passing.

Air.Inst.Ref and Zir.Inst.Ref are separated into different enums but
compile-time verified to have the same fields in the same order.

The large set of changes is mainly to deal with the fact that most Type
and Value methods now require a Module to be passed in, so that the
InternPool object can be accessed.

1 files changed, 0 insertions, 128 deletions

diff --git a/src/target.zig b/src/target.zig
index 5e66c8f417..c89f8ce92c 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -512,134 +512,6 @@ pub fn needUnwindTables(target: std.Target) bool {
     return target.os.tag == .windows;
 }
 
-pub const AtomicPtrAlignmentError = error{
-    FloatTooBig,
-    IntTooBig,
-    BadType,
-};
-
-pub const AtomicPtrAlignmentDiagnostics = struct {
-    bits: u16 = undefined,
-    max_bits: u16 = undefined,
-};
-
-/// If ABI alignment of `ty` is OK for atomic operations, returns 0.
-/// Otherwise returns the alignment required on a pointer for the target
-/// to perform atomic operations.
-// TODO this function does not take into account CPU features, which can affect
-// this value. Audit this!
-pub fn atomicPtrAlignment(
-    target: std.Target,
-    ty: Type,
-    diags: *AtomicPtrAlignmentDiagnostics,
-) AtomicPtrAlignmentError!u32 {
-    const max_atomic_bits: u16 = switch (target.cpu.arch) {
-        .avr,
-        .msp430,
-        .spu_2,
-        => 16,
-
-        .arc,
-        .arm,
-        .armeb,
-        .hexagon,
-        .m68k,
-        .le32,
-        .mips,
-        .mipsel,
-        .nvptx,
-        .powerpc,
-        .powerpcle,
-        .r600,
-        .riscv32,
-        .sparc,
-        .sparcel,
-        .tce,
-        .tcele,
-        .thumb,
-        .thumbeb,
-        .x86,
-        .xcore,
-        .amdil,
-        .hsail,
-        .spir,
-        .kalimba,
-        .lanai,
-        .shave,
-        .wasm32,
-        .renderscript32,
-        .csky,
-        .spirv32,
-        .dxil,
-        .loongarch32,
-        .xtensa,
-        => 32,
-
-        .amdgcn,
-        .bpfel,
-        .bpfeb,
-        .le64,
-        .mips64,
-        .mips64el,
-        .nvptx64,
-        .powerpc64,
-        .powerpc64le,
-        .riscv64,
-        .sparc64,
-        .s390x,
-        .amdil64,
-        .hsail64,
-        .spir64,
-        .wasm64,
-        .renderscript64,
-        .ve,
-        .spirv64,
-        .loongarch64,
-        => 64,
-
-        .aarch64,
-        .aarch64_be,
-        .aarch64_32,
-        => 128,
-
-        .x86_64 => if (std.Target.x86.featureSetHas(target.cpu.features, .cx16)) 128 else 64,
-    };
-
-    var buffer: Type.Payload.Bits = undefined;
-
-    const int_ty = switch (ty.zigTypeTag()) {
-        .Int => ty,
-        .Enum => ty.intTagType(&buffer),
-        .Float => {
-            const bit_count = ty.floatBits(target);
-            if (bit_count > max_atomic_bits) {
-                diags.* = .{
-                    .bits = bit_count,
-                    .max_bits = max_atomic_bits,
-                };
-                return error.FloatTooBig;
-            }
-            return 0;
-        },
-        .Bool => return 0,
-        else => {
-            if (ty.isPtrAtRuntime()) return 0;
-            return error.BadType;
-        },
-    };
-
-    const bit_count = int_ty.intInfo(target).bits;
-    if (bit_count > max_atomic_bits) {
-        diags.* = .{
-            .bits = bit_count,
-            .max_bits = max_atomic_bits,
-        };
-        return error.IntTooBig;
-    }
-
-    return 0;
-}
-
 pub fn defaultAddressSpace(
     target: std.Target,
     context: enum {