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authorDavid Rubin <daviru007@icloud.com>2024-03-13 21:02:15 -0700
committerDavid Rubin <daviru007@icloud.com>2024-05-11 02:17:11 -0700
commit28df64cba45595a201f8c2312656922a8c28a67c (patch)
tree13679895113da1e2fa0199e1b117060bbed880cf /src/target.zig
parent060c475fcd358eb9d05d14ec9f1bb7bfc47e4423 (diff)
downloadzig-28df64cba45595a201f8c2312656922a8c28a67c.tar.gz
zig-28df64cba45595a201f8c2312656922a8c28a67c.zip
riscv: implement `@abs`
- add the `abs` MIR instruction - implement `@abs` by shifting to the right by `bits - 1`, and xoring.
Diffstat (limited to 'src/target.zig')
-rw-r--r--src/target.zig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target.zig b/src/target.zig
index 99b9abcab8..ea58111bc1 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -507,7 +507,7 @@ pub fn zigBackend(target: std.Target, use_llvm: bool) std.builtin.CompilerBacken
if (use_llvm) return .stage2_llvm;
if (target.ofmt == .c) return .stage2_c;
return switch (target.cpu.arch) {
- .wasm32, .wasm64 => std.builtin.CompilerBackend.stage2_wasm,
+ .wasm32, .wasm64 => .stage2_wasm,
.arm, .armeb, .thumb, .thumbeb => .stage2_arm,
.x86_64 => .stage2_x86_64,
.x86 => .stage2_x86,