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authorAndrew Kelley <andrew@ziglang.org>2023-05-15 20:09:54 -0700
committerAndrew Kelley <andrew@ziglang.org>2023-06-10 20:47:53 -0700
commit17882162b3be5542b4e289e5ddc6535a4bb4c6b1 (patch)
tree678a9762bd5894e487ff808562eba690918c23ba /src/target.zig
parent6a9a918fbe4adc23dd7d7573c6f1e499f4be074e (diff)
downloadzig-17882162b3be5542b4e289e5ddc6535a4bb4c6b1.tar.gz
zig-17882162b3be5542b4e289e5ddc6535a4bb4c6b1.zip
stage2: move function types to InternPool
Diffstat (limited to 'src/target.zig')
-rw-r--r--src/target.zig11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/target.zig b/src/target.zig
index c89f8ce92c..ac78d27c1a 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -649,3 +649,14 @@ pub fn compilerRtIntAbbrev(bits: u16) []const u8 {
else => "o", // Non-standard
};
}
+
+pub fn fnCallConvAllowsZigTypes(target: std.Target, cc: std.builtin.CallingConvention) bool {
+ return switch (cc) {
+ .Unspecified, .Async, .Inline => true,
+ // For now we want to authorize PTX kernel to use zig objects, even if
+ // we end up exposing the ABI. The goal is to experiment with more
+ // integrated CPU/GPU code.
+ .Kernel => target.cpu.arch == .nvptx or target.cpu.arch == .nvptx64,
+ else => false,
+ };
+}