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| author | LeRoyce Pearson <leroycepearson@geemili.xyz> | 2020-03-27 11:32:33 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-27 11:32:33 -0600 |
| commit | c7f4e68464e0ebd6e6d0f3230114d189e25e3dc9 (patch) | |
| tree | 1039973f89854e5256d86ecfecc87b2b61be46cd /src/target.cpp | |
| parent | 1a6c3aeec9226eba02655c77872bd01eaa9be711 (diff) | |
| parent | aec4967f36d16cfee43529bd341300f5f77af34a (diff) | |
| download | zig-c7f4e68464e0ebd6e6d0f3230114d189e25e3dc9.tar.gz zig-c7f4e68464e0ebd6e6d0f3230114d189e25e3dc9.zip | |
Merge branch 'master' into feature-file-locks
Diffstat (limited to 'src/target.cpp')
| -rw-r--r-- | src/target.cpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/target.cpp b/src/target.cpp index f0030e05ac..63360fc029 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -66,6 +66,7 @@ static const ZigLLVM_ArchType arch_list[] = { ZigLLVM_wasm64, // WebAssembly with 64-bit pointers ZigLLVM_renderscript32, // 32-bit RenderScript ZigLLVM_renderscript64, // 64-bit RenderScript + ZigLLVM_ve, // NEC SX-Aurora Vector Engine }; static const ZigLLVM_VendorType vendor_list[] = { @@ -139,8 +140,6 @@ static const ZigLLVM_EnvironmentType abi_list[] = { ZigLLVM_CODE16, ZigLLVM_EABI, ZigLLVM_EABIHF, - ZigLLVM_ELFv1, - ZigLLVM_ELFv2, ZigLLVM_Android, ZigLLVM_Musl, ZigLLVM_MuslEABI, @@ -530,6 +529,7 @@ uint32_t target_arch_pointer_bit_width(ZigLLVM_ArchType arch) { case ZigLLVM_spir64: case ZigLLVM_wasm64: case ZigLLVM_renderscript64: + case ZigLLVM_ve: return 64; } zig_unreachable(); @@ -593,6 +593,7 @@ uint32_t target_arch_largest_atomic_bits(ZigLLVM_ArchType arch) { case ZigLLVM_spir64: case ZigLLVM_wasm64: case ZigLLVM_renderscript64: + case ZigLLVM_ve: return 64; case ZigLLVM_x86_64: @@ -889,6 +890,7 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) { case ZigLLVM_xcore: case ZigLLVM_ppc: case ZigLLVM_ppc64: + case ZigLLVM_ve: zig_panic("TODO populate this table with stack pointer register name for this CPU architecture"); } zig_unreachable(); @@ -950,6 +952,7 @@ bool target_is_arm(const ZigTarget *target) { case ZigLLVM_xcore: case ZigLLVM_ppc: case ZigLLVM_ppc64: + case ZigLLVM_ve: return false; } zig_unreachable(); @@ -1188,8 +1191,6 @@ const char *target_libc_generic_name(const ZigTarget *target) { case ZigLLVM_CODE16: case ZigLLVM_EABI: case ZigLLVM_EABIHF: - case ZigLLVM_ELFv1: - case ZigLLVM_ELFv2: case ZigLLVM_Android: case ZigLLVM_MSVC: case ZigLLVM_Itanium: @@ -1238,7 +1239,8 @@ void target_libc_enum(size_t index, ZigTarget *out_target) { out_target->os = libcs_available[index].os; out_target->abi = libcs_available[index].abi; out_target->vendor = ZigLLVM_UnknownVendor; - out_target->is_native = false; + out_target->is_native_os = false; + out_target->is_native_cpu = false; } bool target_has_debug_info(const ZigTarget *target) { |