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authorJakub Konka <kubkon@jakubkonka.com>2021-09-13 23:12:19 +0200
committerJakub Konka <kubkon@jakubkonka.com>2021-09-13 23:40:38 +0200
commita38b636045c0384faad1565d47dfbf774821021e (patch)
treea78193473fd5b725feaf2762b10cfc189a26a325 /src/stage1/ir.cpp
parent760241ce50eaa9031339f6b591358b53f5797486 (diff)
parentf011f13933b72f4d63a5f635c7646b68beee726e (diff)
downloadzig-a38b636045c0384faad1565d47dfbf774821021e.tar.gz
zig-a38b636045c0384faad1565d47dfbf774821021e.zip
Merge remote-tracking branch 'origin/master' into zld-incr
Diffstat (limited to 'src/stage1/ir.cpp')
-rw-r--r--src/stage1/ir.cpp36
1 files changed, 36 insertions, 0 deletions
diff --git a/src/stage1/ir.cpp b/src/stage1/ir.cpp
index 830ce76708..0604c05c46 100644
--- a/src/stage1/ir.cpp
+++ b/src/stage1/ir.cpp
@@ -9820,6 +9820,34 @@ static ErrorMsg *ir_eval_math_op_scalar(IrAnalyze *ira, Scope *scope, AstNode *s
float_min(out_val, op1_val, op2_val);
}
break;
+ case IrBinOpSatAdd:
+ if (is_int) {
+ bigint_add_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
+ } else {
+ zig_unreachable();
+ }
+ break;
+ case IrBinOpSatSub:
+ if (is_int) {
+ bigint_sub_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
+ } else {
+ zig_unreachable();
+ }
+ break;
+ case IrBinOpSatMul:
+ if (is_int) {
+ bigint_mul_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
+ } else {
+ zig_unreachable();
+ }
+ break;
+ case IrBinOpSatShl:
+ if (is_int) {
+ bigint_shl_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
+ } else {
+ zig_unreachable();
+ }
+ break;
}
if (type_entry->id == ZigTypeIdInt) {
@@ -10041,6 +10069,10 @@ static bool ok_float_op(IrBinOp op) {
case IrBinOpBitShiftRightExact:
case IrBinOpAddWrap:
case IrBinOpSubWrap:
+ case IrBinOpSatAdd:
+ case IrBinOpSatSub:
+ case IrBinOpSatMul:
+ case IrBinOpSatShl:
case IrBinOpMultWrap:
case IrBinOpArrayCat:
case IrBinOpArrayMult:
@@ -11014,6 +11046,10 @@ static Stage1AirInst *ir_analyze_instruction_bin_op(IrAnalyze *ira, Stage1ZirIns
case IrBinOpRemMod:
case IrBinOpMaximum:
case IrBinOpMinimum:
+ case IrBinOpSatAdd:
+ case IrBinOpSatSub:
+ case IrBinOpSatMul:
+ case IrBinOpSatShl:
return ir_analyze_bin_op_math(ira, bin_op_instruction);
case IrBinOpArrayCat:
return ir_analyze_array_cat(ira, bin_op_instruction);