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| author | Andrew Kelley <andrew@ziglang.org> | 2019-06-12 18:08:56 -0400 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2019-06-12 18:08:56 -0400 |
| commit | e6fa2ee70632ef1efbe3ebc54214abf30d6d40c1 (patch) | |
| tree | d9185c839d2efae13b5a7a35e34364914a7a52b7 /src/main.cpp | |
| parent | 1526d89711c90a4a98dfecb6d3c64f28c3ab7da6 (diff) | |
| download | zig-e6fa2ee70632ef1efbe3ebc54214abf30d6d40c1.tar.gz zig-e6fa2ee70632ef1efbe3ebc54214abf30d6d40c1.zip | |
fix nested peer result locs with no memory loc
```zig
export fn entry2(c: bool) i32 {
return if (c)
i32(0)
else if (c)
i32(1)
else
i32(2);
}
```
```llvm
define i32 @entry2(i1) #2 !dbg !35 {
Entry:
%c = alloca i1, align 1
store i1 %0, i1* %c, align 1
call void @llvm.dbg.declare(metadata i1* %c, metadata !41, metadata !DIExpression()), !dbg !42
%1 = load i1, i1* %c, align 1, !dbg !43
br i1 %1, label %Then, label %Else, !dbg !43
Then: ; preds = %Entry
br label %EndIf3, !dbg !45
Else: ; preds = %Entry
%2 = load i1, i1* %c, align 1, !dbg !46
br i1 %2, label %Then1, label %Else2, !dbg !46
Then1: ; preds = %Else
br label %EndIf, !dbg !47
Else2: ; preds = %Else
br label %EndIf, !dbg !47
EndIf: ; preds = %Else2, %Then1
%3 = phi i32 [ 1, %Then1 ], [ 2, %Else2 ], !dbg !47
br label %EndIf3, !dbg !45
EndIf3: ; preds = %EndIf, %Then
%4 = phi i32 [ 0, %Then ], [ %3, %EndIf ], !dbg !45
ret i32 %4, !dbg !48
}
```
Diffstat (limited to 'src/main.cpp')
0 files changed, 0 insertions, 0 deletions