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| author | Veikka Tuominen <git@vexu.eu> | 2023-05-26 23:29:05 +0300 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2023-05-26 21:42:19 -0700 |
| commit | ca16f1e8a703491bcaac0d13379d2556e8ca837d (patch) | |
| tree | fefadd0912e8e3deedbf0a7261219fbd7ee5149f /src/link/Plan9.zig | |
| parent | dbd44658ff2d392451ea4f3a38ca4bd26da34314 (diff) | |
| download | zig-ca16f1e8a703491bcaac0d13379d2556e8ca837d.tar.gz zig-ca16f1e8a703491bcaac0d13379d2556e8ca837d.zip | |
std.Target adjustments
* move `ptrBitWidth` from Arch to Target since it needs to know about the abi
* double isn't always 8 bits
* AVR uses 1-byte alignment for everything in GCC
Diffstat (limited to 'src/link/Plan9.zig')
| -rw-r--r-- | src/link/Plan9.zig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/link/Plan9.zig b/src/link/Plan9.zig index bef06d1c87..a785f084cb 100644 --- a/src/link/Plan9.zig +++ b/src/link/Plan9.zig @@ -183,7 +183,7 @@ pub fn defaultBaseAddrs(arch: std.Target.Cpu.Arch) Bases { pub fn createEmpty(gpa: Allocator, options: link.Options) !*Plan9 { if (options.use_llvm) return error.LLVMBackendDoesNotSupportPlan9; - const sixtyfour_bit: bool = switch (options.target.cpu.arch.ptrBitWidth()) { + const sixtyfour_bit: bool = switch (options.target.ptrBitWidth()) { 0...32 => false, 33...64 => true, else => return error.UnsupportedP9Architecture, |