start adding big endian RISC-V support

The big endian RISC-V effort is mostly driven by MIPS (the company) which is
pivoting to RISC-V, and presumably needs a big endian variant to fill the niche
that big endian MIPS (the ISA) did.

GCC already supports these targets, but LLVM support will only appear in 22;
this commit just adds the necessary target knowledge and checks on our end.

1 files changed, 10 insertions, 10 deletions

diff --git a/src/link/Elf/relocation.zig b/src/link/Elf/relocation.zig
index 366d19d9b3..9271d07ae1 100644
--- a/src/link/Elf/relocation.zig
+++ b/src/link/Elf/relocation.zig
@@ -76,8 +76,8 @@ const riscv64_relocs = Table(11, elf.R_RISCV, .{
 pub fn decode(r_type: u32, cpu_arch: std.Target.Cpu.Arch) ?Kind {
     return switch (cpu_arch) {
         .x86_64 => x86_64_relocs.decode(r_type),
-        .aarch64 => aarch64_relocs.decode(r_type),
-        .riscv64 => riscv64_relocs.decode(r_type),
+        .aarch64, .aarch64_be => aarch64_relocs.decode(r_type),
+        .riscv64, .riscv64be => riscv64_relocs.decode(r_type),
         else => @panic("TODO unhandled cpu arch"),
     };
 }
@@ -85,8 +85,8 @@ pub fn decode(r_type: u32, cpu_arch: std.Target.Cpu.Arch) ?Kind {
 pub fn encode(comptime kind: Kind, cpu_arch: std.Target.Cpu.Arch) u32 {
     return switch (cpu_arch) {
         .x86_64 => x86_64_relocs.encode(kind),
-        .aarch64 => aarch64_relocs.encode(kind),
-        .riscv64 => riscv64_relocs.encode(kind),
+        .aarch64, .aarch64_be => aarch64_relocs.encode(kind),
+        .riscv64, .riscv64be => riscv64_relocs.encode(kind),
         else => @panic("TODO unhandled cpu arch"),
     };
 }
@@ -98,11 +98,11 @@ pub const dwarf = struct {
                 .@"32" => .@"32",
                 .@"64" => .@"64",
             })),
-            .aarch64 => @intFromEnum(@as(elf.R_AARCH64, switch (format) {
+            .aarch64, .aarch64_be => @intFromEnum(@as(elf.R_AARCH64, switch (format) {
                 .@"32" => .ABS32,
                 .@"64" => .ABS64,
             })),
-            .riscv64 => @intFromEnum(@as(elf.R_RISCV, switch (format) {
+            .riscv64, .riscv64be => @intFromEnum(@as(elf.R_RISCV, switch (format) {
                 .@"32" => .@"32",
                 .@"64" => .@"64",
             })),
@@ -125,7 +125,7 @@ pub const dwarf = struct {
                 },
                 .debug_frame => .PC32,
             })),
-            .aarch64 => @intFromEnum(@as(elf.R_AARCH64, switch (source_section) {
+            .aarch64, .aarch64_be => @intFromEnum(@as(elf.R_AARCH64, switch (source_section) {
                 else => switch (address_size) {
                     .@"32" => .ABS32,
                     .@"64" => .ABS64,
@@ -133,7 +133,7 @@ pub const dwarf = struct {
                 },
                 .debug_frame => .PREL32,
             })),
-            .riscv64 => @intFromEnum(@as(elf.R_RISCV, switch (source_section) {
+            .riscv64, .riscv64be => @intFromEnum(@as(elf.R_RISCV, switch (source_section) {
                 else => switch (address_size) {
                     .@"32" => .@"32",
                     .@"64" => .@"64",
@@ -164,8 +164,8 @@ fn formatRelocType(ctx: FormatRelocTypeCtx, writer: *std.io.Writer) std.io.Write
     const r_type = ctx.r_type;
     switch (ctx.cpu_arch) {
         .x86_64 => try writer.print("R_X86_64_{s}", .{@tagName(@as(elf.R_X86_64, @enumFromInt(r_type)))}),
-        .aarch64 => try writer.print("R_AARCH64_{s}", .{@tagName(@as(elf.R_AARCH64, @enumFromInt(r_type)))}),
-        .riscv64 => try writer.print("R_RISCV_{s}", .{@tagName(@as(elf.R_RISCV, @enumFromInt(r_type)))}),
+        .aarch64, .aarch64_be => try writer.print("R_AARCH64_{s}", .{@tagName(@as(elf.R_AARCH64, @enumFromInt(r_type)))}),
+        .riscv64, .riscv64be => try writer.print("R_RISCV_{s}", .{@tagName(@as(elf.R_RISCV, @enumFromInt(r_type)))}),
         else => unreachable,
     }
 }