diff options
| author | Andrew Kelley <andrew@ziglang.org> | 2020-01-26 09:57:25 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-26 09:57:25 -0500 |
| commit | 96e5f476c3f7f44d0b299bc6043f3fd88769bd8b (patch) | |
| tree | 5aadd86ef359eb847bf842f9594690737f0e67c4 /src/ir.cpp | |
| parent | 4e9b1f5479e3b7ce47d059e0e6f3d62cd4ee7254 (diff) | |
| parent | 3839ea89785856bbed0624a6a18eb6e5acfb46c3 (diff) | |
| download | zig-96e5f476c3f7f44d0b299bc6043f3fd88769bd8b.tar.gz zig-96e5f476c3f7f44d0b299bc6043f3fd88769bd8b.zip | |
Merge pull request #4264 from ziglang/layneson-cpus_and_features
Add support for target details (CPUs and their supported features)
Diffstat (limited to 'src/ir.cpp')
| -rw-r--r-- | src/ir.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/ir.cpp b/src/ir.cpp index 2188286bb7..b24cf3828e 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -23262,7 +23262,11 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc return ira->codegen->invalid_inst_gen; } - assert(target->value->type->id == ZigTypeIdEnum); + if (target->value->type->id != ZigTypeIdEnum) { + ir_add_error(ira, &target->base, + buf_sprintf("expected enum tag, found '%s'", buf_ptr(&target->value->type->name))); + return ira->codegen->invalid_inst_gen; + } if (target->value->type->data.enumeration.src_field_count == 1 && !target->value->type->data.enumeration.non_exhaustive) { |