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| author | Vexu <15308111+Vexu@users.noreply.github.com> | 2019-08-17 22:51:25 +0300 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2019-08-17 16:05:41 -0400 |
| commit | 0ff396c34f93b60a000e1ee50e881a8c25122b79 (patch) | |
| tree | 6d135970e8f427cc43dc438a5b9b96a967c43264 /src/ir.cpp | |
| parent | 4d8a6f6fea1b6922e7904b33c5b575249213fe53 (diff) | |
| download | zig-0ff396c34f93b60a000e1ee50e881a8c25122b79.tar.gz zig-0ff396c34f93b60a000e1ee50e881a8c25122b79.zip | |
add compile error for incorrect atomic ordering in fence #3082
Diffstat (limited to 'src/ir.cpp')
| -rw-r--r-- | src/ir.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/ir.cpp b/src/ir.cpp index 15c570ddd9..51f849ce19 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -20860,6 +20860,12 @@ static IrInstruction *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstruction if (!ir_resolve_atomic_order(ira, order_value, &order)) return ira->codegen->invalid_instruction; + if (order < AtomicOrderAcquire) { + ir_add_error(ira, order_value, + buf_sprintf("atomic ordering must be Acquire or stricter")); + return ira->codegen->invalid_instruction; + } + IrInstruction *result = ir_build_fence(&ira->new_irb, instruction->base.scope, instruction->base.source_node, order_value, order); result->value.type = ira->codegen->builtin_types.entry_void; |