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| author | David Rubin <daviru007@icloud.com> | 2024-03-17 17:45:20 -0700 |
|---|---|---|
| committer | David Rubin <daviru007@icloud.com> | 2024-05-11 02:17:11 -0700 |
| commit | 9b2a4582c983a4171de9ab9843d0af1d807ddbff (patch) | |
| tree | d48479067b383ab4e7ef1ff30d53eca7e3e33e8a /src/codegen | |
| parent | f67fa73fe8bc5cc38af826c396d912b7f72b3261 (diff) | |
| download | zig-9b2a4582c983a4171de9ab9843d0af1d807ddbff.tar.gz zig-9b2a4582c983a4171de9ab9843d0af1d807ddbff.zip | |
riscv: implement 64 bit immediate into register loading
LLVM has a better myriad sequence for this, where they don't allocate
a temporary register, but for now this will do.
Diffstat (limited to 'src/codegen')
0 files changed, 0 insertions, 0 deletions