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| author | David Rubin <daviru007@icloud.com> | 2024-03-22 20:14:10 -0700 |
|---|---|---|
| committer | David Rubin <daviru007@icloud.com> | 2024-05-11 02:17:11 -0700 |
| commit | 5e010b6deac7ad34f0cd06d507fc468fd98f9abc (patch) | |
| tree | d331bfc3ab68221d9e8f569d8b30f0e3374491d5 /src/codegen | |
| parent | 63bbf665538d927bd56646e063821e31577f83f5 (diff) | |
| download | zig-5e010b6deac7ad34f0cd06d507fc468fd98f9abc.tar.gz zig-5e010b6deac7ad34f0cd06d507fc468fd98f9abc.zip | |
riscv: reorganize `binOp` and implement `cmp_imm_gte` MIR
this was an annoying one to do, as there is no (to my knowledge) myriad sequence
that will allow us to do `gte` compares with an immediate without allocating a register.
RISC-V provides a single instruction to do compares, that being `lt`, and so you need to
use more than one for other variants, but in this case, i believe you need to allocate a register.
Diffstat (limited to 'src/codegen')
0 files changed, 0 insertions, 0 deletions