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| author | Frank Denis <124872+jedisct1@users.noreply.github.com> | 2024-11-22 10:00:49 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-22 10:00:49 +0100 |
| commit | 636308a17d8f8118ab34e9d4b217baa5878416c4 (patch) | |
| tree | d686f3b2cb237c0f6d4a75cf3b22760ae113ac16 /src/codegen/spirv/Module.zig | |
| parent | f845fa04a0dce3104efe129c73a6ad792b1712b6 (diff) | |
| download | zig-636308a17d8f8118ab34e9d4b217baa5878416c4.tar.gz zig-636308a17d8f8118ab34e9d4b217baa5878416c4.zip | |
std.crypto.aes: introduce AES block vectors (#22023)
* std.crypto.aes: introduce AES block vectors
Modern Intel CPUs with the VAES extension can handle more than a
single AES block per instruction.
So can some ARM and RISC-V CPUs. Software implementations with
bitslicing can also greatly benefit from this.
Implement low-level operations on AES block vectors, and the
parallel AEGIS variants on top of them.
AMD Zen4:
aegis-128x4: 73225 MiB/s
aegis-128x2: 51571 MiB/s
aegis-128l: 25806 MiB/s
aegis-256x4: 46742 MiB/s
aegis-256x2: 30227 MiB/s
aegis-256: 8436 MiB/s
aes128-gcm: 5926 MiB/s
aes256-gcm: 5085 MiB/s
AES-GCM, and anything based on AES-CTR are also going to benefit
from this later.
* Make AEGIS-MAC twice a fast
Diffstat (limited to 'src/codegen/spirv/Module.zig')
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