aboutsummaryrefslogtreecommitdiff
path: root/src/codegen/spirv.zig
diff options
context:
space:
mode:
authorAndrew Kelley <andrew@ziglang.org>2022-12-03 00:42:11 -0500
committerGitHub <noreply@github.com>2022-12-03 00:42:11 -0500
commitfdbb0fb7b9c08ebff1b7e45ef89f7160f350d44c (patch)
tree714f2766c64ace45df1f7d67ca70be0c88193184 /src/codegen/spirv.zig
parentc43ac67f82cb5a022df67729aa1e6bebc22cfff2 (diff)
parentb500e0eb179218f5eb03408c09b5e5a928f0c46e (diff)
downloadzig-fdbb0fb7b9c08ebff1b7e45ef89f7160f350d44c.tar.gz
zig-fdbb0fb7b9c08ebff1b7e45ef89f7160f350d44c.zip
Merge pull request #13744 from Vexu/stage2-fixes
Improve error messages, fix dependency loops
Diffstat (limited to 'src/codegen/spirv.zig')
-rw-r--r--src/codegen/spirv.zig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/codegen/spirv.zig b/src/codegen/spirv.zig
index ada3918baf..bd0c8bc53c 100644
--- a/src/codegen/spirv.zig
+++ b/src/codegen/spirv.zig
@@ -360,7 +360,7 @@ pub const DeclGen = struct {
// Note, value is required to be sign-extended, so we don't need to mask off the upper bits.
// See https://www.khronos.org/registry/SPIR-V/specs/unified1/SPIRV.html#Literal
- var int_bits = if (ty.isSignedInt()) @bitCast(u64, val.toSignedInt()) else val.toUnsignedInt(target);
+ var int_bits = if (ty.isSignedInt()) @bitCast(u64, val.toSignedInt(target)) else val.toUnsignedInt(target);
const value: spec.LiteralContextDependentNumber = switch (backing_bits) {
1...32 => .{ .uint32 = @truncate(u32, int_bits) },
@@ -763,7 +763,7 @@ pub const DeclGen = struct {
if (elem.isUndef()) {
self.func.body.writeOperand(spec.LiteralInteger, 0xFFFF_FFFF);
} else {
- const int = elem.toSignedInt();
+ const int = elem.toSignedInt(self.getTarget());
const unsigned = if (int >= 0) @intCast(u32, int) else @intCast(u32, ~int + a_len);
self.func.body.writeOperand(spec.LiteralInteger, unsigned);
}