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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-09-17 17:24:07 +0200 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-09-18 12:42:24 +0200 |
| commit | 5e9e1fb0c85eacd412cb6cf4df14adc39f4c008a (patch) | |
| tree | 6e8682d6f3571d5e7091561f3bf2389776af2e10 /src/codegen/mips | |
| parent | 6208e74145791c2f03e80e93caec4f87c60e638f (diff) | |
| download | zig-5e9e1fb0c85eacd412cb6cf4df14adc39f4c008a.tar.gz zig-5e9e1fb0c85eacd412cb6cf4df14adc39f4c008a.zip | |
std.Target: adjustments to LoongArch CPU models
* Remove the generic model; we already have generic_la32 and generic_la64 and
pick appropriately based on bitness.
* Remove the loongarch64 model. We used this as our baseline for 64-bit, but it's
actually pretty misleading and useless; it doesn't represent any real CPU and
has less features than generic_la64.
* Add la64v1_0 and la64v1_1 models.
* Change our baseline CPU model for 64-bit to be la64v1_0, thus adding LSX to
the baseline feature set.
Diffstat (limited to 'src/codegen/mips')
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