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| author | Robin Voetter <robin@voetter.nl> | 2024-08-14 04:14:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-14 04:14:34 +0200 |
| commit | 1018cdc0a8d0bdd9c90cf09fed5a38f510f97b62 (patch) | |
| tree | 38c11449e17222199c11afb30f942437498a3142 /src/codegen/llvm | |
| parent | 0b5ea2b902b5802786cac70740e93872d2a0973d (diff) | |
| parent | bcfc7cf13cd3eb16f4b864efac5269d68200b070 (diff) | |
| download | zig-1018cdc0a8d0bdd9c90cf09fed5a38f510f97b62.tar.gz zig-1018cdc0a8d0bdd9c90cf09fed5a38f510f97b62.zip | |
Merge pull request #21030 from Snektron/nv-gpu-builtins
nvptx: add implementations for GPU builtins
Diffstat (limited to 'src/codegen/llvm')
| -rw-r--r-- | src/codegen/llvm/Builder.zig | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/src/codegen/llvm/Builder.zig b/src/codegen/llvm/Builder.zig index a23bc86c57..90da3bdd7a 100644 --- a/src/codegen/llvm/Builder.zig +++ b/src/codegen/llvm/Builder.zig @@ -2729,6 +2729,17 @@ pub const Intrinsic = enum { @"amdgcn.workgroup.id.z", @"amdgcn.dispatch.ptr", + // NVPTX + @"nvvm.read.ptx.sreg.tid.x", + @"nvvm.read.ptx.sreg.tid.y", + @"nvvm.read.ptx.sreg.tid.z", + @"nvvm.read.ptx.sreg.ntid.x", + @"nvvm.read.ptx.sreg.ntid.y", + @"nvvm.read.ptx.sreg.ntid.z", + @"nvvm.read.ptx.sreg.ctaid.x", + @"nvvm.read.ptx.sreg.ctaid.y", + @"nvvm.read.ptx.sreg.ctaid.z", + // WebAssembly @"wasm.memory.size", @"wasm.memory.grow", @@ -3886,6 +3897,72 @@ pub const Intrinsic = enum { .attrs = &.{ .nocallback, .nofree, .nosync, .nounwind, .speculatable, .willreturn, .{ .memory = Attribute.Memory.all(.none) } }, }, + .@"nvvm.read.ptx.sreg.tid.x" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + .@"nvvm.read.ptx.sreg.tid.y" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + .@"nvvm.read.ptx.sreg.tid.z" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + + .@"nvvm.read.ptx.sreg.ntid.x" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + .@"nvvm.read.ptx.sreg.ntid.y" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + .@"nvvm.read.ptx.sreg.ntid.z" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + + .@"nvvm.read.ptx.sreg.ctaid.x" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + .@"nvvm.read.ptx.sreg.ctaid.y" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + .@"nvvm.read.ptx.sreg.ctaid.z" = .{ + .ret_len = 1, + .params = &.{ + .{ .kind = .{ .type = .i32 } }, + }, + .attrs = &.{ .nounwind, .readnone }, + }, + .@"wasm.memory.size" = .{ .ret_len = 1, .params = &.{ |