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| author | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2021-01-17 22:22:47 +0100 |
|---|---|---|
| committer | joachimschmidt557 <joachim.schmidt557@outlook.com> | 2021-01-17 22:22:47 +0100 |
| commit | c6cb02c2265f181baaae4d57679baa8306431c11 (patch) | |
| tree | 54b3eb169ba2f694b7a94da9d274667f4739ee2e /src/codegen.zig | |
| parent | 3562edf13772bca66b4f04fc87be25b518393221 (diff) | |
| download | zig-c6cb02c2265f181baaae4d57679baa8306431c11.tar.gz zig-c6cb02c2265f181baaae4d57679baa8306431c11.zip | |
stage2 AArch64: fix stack offsets in genSetStack
Diffstat (limited to 'src/codegen.zig')
| -rw-r--r-- | src/codegen.zig | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/codegen.zig b/src/codegen.zig index 1478ede6ff..df04a740b9 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -2693,9 +2693,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { switch (abi_size) { 1, 4 => { - const offset = if (adj_off <= math.maxInt(u12)) blk: { - break :blk Instruction.Offset.imm(@intCast(u12, adj_off)); - } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0); + const offset = if (math.cast(u12, adj_off)) |imm| blk: { + break :blk Instruction.Offset.imm(imm); + } else |_| Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0); const str = switch (abi_size) { 1 => Instruction.strb, 4 => Instruction.str, @@ -2856,12 +2856,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { switch (abi_size) { 4, 8 => { - const offset = if (adj_off <= math.maxInt(u12)) blk: { - break :blk Instruction.LoadStoreOffset.imm(@intCast(u12, adj_off)); - } else Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off })); - const rn: Register = switch (abi_size) { - 4 => .w29, - 8 => .x29, + const offset = if (math.cast(i9, adj_off)) |imm| + Instruction.LoadStoreOffset.imm_post_index(-imm) + else |_| + Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off })); + const rn: Register = switch (arch) { + .aarch64, .aarch64_be => .x29, + .aarch64_32 => .w29, else => unreachable, }; |