stage2: sparc64: Implement SPARCv9 movr

2 files changed, 29 insertions, 1 deletions

diff --git a/src/arch/sparc64/Emit.zig b/src/arch/sparc64/Emit.zig
index 937431afae..ac7fd89d00 100644
--- a/src/arch/sparc64/Emit.zig
+++ b/src/arch/sparc64/Emit.zig
@@ -102,7 +102,7 @@ pub fn emitMir(
 
             .movcc => try emit.mirConditionalMove(inst),
 
-            .movr => @panic("TODO implement sparc64 movr"),
+            .movr => try emit.mirConditionalMove(inst),
 
             .mulx => try emit.mirArithmetic3Op(inst),
             .sdivx => try emit.mirArithmetic3Op(inst),
@@ -346,6 +346,26 @@ fn mirConditionalMove(emit: *Emit, inst: Mir.Inst.Index) !void {
                 ));
             }
         },
+        .movr => {
+            const data = emit.mir.instructions.items(.data)[inst].conditional_move_reg;
+            if (data.is_imm) {
+                try emit.writeInstruction(Instruction.movr(
+                    i10,
+                    data.cond,
+                    data.rs1,
+                    data.rs2_or_imm.imm,
+                    data.rd,
+                ));
+            } else {
+                try emit.writeInstruction(Instruction.movr(
+                    Register,
+                    data.cond,
+                    data.rs1,
+                    data.rs2_or_imm.rs2,
+                    data.rd,
+                ));
+            }
+        },
         else => unreachable,
     }
 }
diff --git a/src/arch/sparc64/bits.zig b/src/arch/sparc64/bits.zig
index 4c1a641d45..ebfc55635c 100644
--- a/src/arch/sparc64/bits.zig
+++ b/src/arch/sparc64/bits.zig
@@ -1273,6 +1273,14 @@ pub const Instruction = union(enum) {
         };
     }
 
+    pub fn movr(comptime s2: type, cond: RCondition, rs1: Register, rs2: s2, rd: Register) Instruction {
+        return switch (s2) {
+            Register => format3e(0b10, 0b10_1111, cond, rs1, rs2, rd),
+            i10 => format3f(0b10, 0b10_1111, cond, rs1, rs2, rd),
+            else => unreachable,
+        };
+    }
+
     pub fn mulx(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
         return switch (s2) {
             Register => format3a(0b10, 0b00_1001, rs1, rs2, rd),