Merge pull request #18017 from mlugg/var-never-mutated

compiler: add error for unnecessary use of 'var'

7 files changed, 18 insertions, 10 deletions

diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
index 0e56a1cda1..c52fc33915 100644
--- a/src/arch/riscv64/CodeGen.zig
+++ b/src/arch/riscv64/CodeGen.zig
@@ -2648,6 +2648,11 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
             // conventions
             var next_register: usize = 0;
             var next_stack_offset: u32 = 0;
+            // TODO: this is never assigned, which is a bug, but I don't know how this code works
+            // well enough to try and fix it. I *think* `next_register += next_stack_offset` is
+            // supposed to be `next_stack_offset += param_size` in every case where it appears.
+            _ = &next_stack_offset;
+
             const argument_registers = [_]Register{ .a0, .a1, .a2, .a3, .a4, .a5, .a6, .a7 };
 
             for (fn_info.param_types.get(ip), result.args) |ty, *result_arg| {
diff --git a/src/arch/sparc64/CodeGen.zig b/src/arch/sparc64/CodeGen.zig
index 40f134ec90..be624c8d95 100644
--- a/src/arch/sparc64/CodeGen.zig
+++ b/src/arch/sparc64/CodeGen.zig
@@ -4481,6 +4481,10 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type, role: RegisterView)
 
             var next_register: usize = 0;
             var next_stack_offset: u32 = 0;
+            // TODO: this is never assigned, which is a bug, but I don't know how this code works
+            // well enough to try and fix it. I *think* `next_register += next_stack_offset` is
+            // supposed to be `next_stack_offset += param_size` in every case where it appears.
+            _ = &next_stack_offset;
 
             // The caller puts the argument in %o0-%o5, which becomes %i0-%i5 inside the callee.
             const argument_registers = switch (role) {
diff --git a/src/arch/wasm/CodeGen.zig b/src/arch/wasm/CodeGen.zig
index 7c752490c6..da0226b54c 100644
--- a/src/arch/wasm/CodeGen.zig
+++ b/src/arch/wasm/CodeGen.zig
@@ -2139,7 +2139,7 @@ fn airRetPtr(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
     const mod = func.bin_file.base.options.module.?;
     const child_type = func.typeOfIndex(inst).childType(mod);
 
-    var result = result: {
+    const result = result: {
         if (!child_type.isFnOrHasRuntimeBitsIgnoreComptime(mod)) {
             break :result try func.allocStack(Type.usize); // create pointer to void
         }
@@ -5001,7 +5001,7 @@ fn airArrayElemVal(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
                 return func.finishAir(inst, try WValue.toLocal(.stack, func, elem_ty), &.{ bin_op.lhs, bin_op.rhs });
             },
             else => {
-                var stack_vec = try func.allocStack(array_ty);
+                const stack_vec = try func.allocStack(array_ty);
                 try func.store(stack_vec, array, array_ty, 0);
 
                 // Is a non-unrolled vector (v128)
@@ -5944,7 +5944,7 @@ fn airAddSubWithOverflow(func: *CodeGen, inst: Air.Inst.Index, op: Op) InnerErro
         rhs.free(func);
     };
 
-    var bin_op = try (try func.binOp(lhs, rhs, lhs_ty, op)).toLocal(func, lhs_ty);
+    const bin_op = try (try func.binOp(lhs, rhs, lhs_ty, op)).toLocal(func, lhs_ty);
     var result = if (wasm_bits != int_info.bits) blk: {
         break :blk try (try func.wrapOperand(bin_op, lhs_ty)).toLocal(func, lhs_ty);
     } else bin_op;
@@ -6335,7 +6335,7 @@ fn airMulAdd(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
         const lhs_ext = try func.fpext(lhs, ty, Type.f32);
         const addend_ext = try func.fpext(addend, ty, Type.f32);
         // call to compiler-rt `fn fmaf(f32, f32, f32) f32`
-        var result = try func.callIntrinsic(
+        const result = try func.callIntrinsic(
             "fmaf",
             &.{ .f32_type, .f32_type, .f32_type },
             Type.f32,
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index 822ff0ec2d..ed3863462b 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -2181,7 +2181,7 @@ fn genLazy(self: *Self, lazy_sym: link.File.LazySymbol) InnerError!void {
             const ret_reg = param_regs[0];
             const enum_mcv = MCValue{ .register = param_regs[1] };
 
-            var exitlude_jump_relocs = try self.gpa.alloc(Mir.Inst.Index, enum_ty.enumFieldCount(mod));
+            const exitlude_jump_relocs = try self.gpa.alloc(Mir.Inst.Index, enum_ty.enumFieldCount(mod));
             defer self.gpa.free(exitlude_jump_relocs);
 
             const data_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
diff --git a/src/arch/x86_64/Disassembler.zig b/src/arch/x86_64/Disassembler.zig
index b15327fd21..e0117fa17b 100644
--- a/src/arch/x86_64/Disassembler.zig
+++ b/src/arch/x86_64/Disassembler.zig
@@ -234,13 +234,12 @@ fn inst(encoding: Encoding, args: struct {
     op3: Instruction.Operand = .none,
     op4: Instruction.Operand = .none,
 }) Instruction {
-    var i = Instruction{ .encoding = encoding, .prefix = args.prefix, .ops = .{
+    return .{ .encoding = encoding, .prefix = args.prefix, .ops = .{
         args.op1,
         args.op2,
         args.op3,
         args.op4,
     } };
-    return i;
 }
 
 const Prefixes = struct {
diff --git a/src/arch/x86_64/Lower.zig b/src/arch/x86_64/Lower.zig
index b26cbe1503..0c309991f6 100644
--- a/src/arch/x86_64/Lower.zig
+++ b/src/arch/x86_64/Lower.zig
@@ -342,7 +342,7 @@ fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand)
         .Lib => lower.bin_file.options.link_mode == .Static,
     };
 
-    var emit_prefix = prefix;
+    const emit_prefix = prefix;
     var emit_mnemonic = mnemonic;
     var emit_ops_storage: [4]Operand = undefined;
     const emit_ops = emit_ops_storage[0..ops.len];
diff --git a/src/arch/x86_64/encoder.zig b/src/arch/x86_64/encoder.zig
index 517dd1af8d..b499ccfdca 100644
--- a/src/arch/x86_64/encoder.zig
+++ b/src/arch/x86_64/encoder.zig
@@ -244,7 +244,7 @@ pub const Instruction = struct {
                     }),
                 },
                 .imm => |imm| if (enc_op.isSigned()) {
-                    var imms = imm.asSigned(enc_op.immBitSize());
+                    const imms = imm.asSigned(enc_op.immBitSize());
                     if (imms < 0) try writer.writeByte('-');
                     try writer.print("0x{x}", .{@abs(imms)});
                 } else try writer.print("0x{x}", .{imm.asUnsigned(enc_op.immBitSize())}),
@@ -1077,7 +1077,7 @@ fn expectEqualHexStrings(expected: []const u8, given: []const u8, assembly: []co
     const given_fmt = try std.fmt.allocPrint(testing.allocator, "{x}", .{std.fmt.fmtSliceHexLower(given)});
     defer testing.allocator.free(given_fmt);
     const idx = std.mem.indexOfDiff(u8, expected_fmt, given_fmt).?;
-    var padding = try testing.allocator.alloc(u8, idx + 5);
+    const padding = try testing.allocator.alloc(u8, idx + 5);
     defer testing.allocator.free(padding);
     @memset(padding, ' ');
     std.debug.print("\nASM: {s}\nEXP: {s}\nGIV: {s}\n{s}^ -- first differing byte\n", .{