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| author | Jacob Young <jacobly0@users.noreply.github.com> | 2023-10-08 02:13:33 -0400 |
|---|---|---|
| committer | Jacob Young <jacobly0@users.noreply.github.com> | 2023-10-08 04:41:55 -0400 |
| commit | 3bf9a8feb50c3ff20da80593a735ec3244cb5d89 (patch) | |
| tree | ee53ac71cb9fbed67b0daa5487030d430b8dd842 /src/arch | |
| parent | 9fc9235ac815f8b0ad88445216407a0a9f747d5f (diff) | |
| download | zig-3bf9a8feb50c3ff20da80593a735ec3244cb5d89.tar.gz zig-3bf9a8feb50c3ff20da80593a735ec3244cb5d89.zip | |
x86_64: fix `@divTrunc` and `@divFloor` of `f16`
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86_64/CodeGen.zig | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index bdad8312d5..46682345b9 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -7177,6 +7177,23 @@ fn genBinOp( dst_reg, tmp_reg, ); + switch (air_tag) { + .div_trunc, .div_floor => try self.asmRegisterRegisterRegisterImmediate( + .{ .v_ss, .round }, + dst_reg, + dst_reg, + dst_reg, + Immediate.u(@as(u5, @bitCast(RoundMode{ + .mode = switch (air_tag) { + .div_trunc => .zero, + .div_floor => .down, + else => unreachable, + }, + .precision = .inexact, + }))), + ), + else => {}, + } try self.asmRegisterRegisterImmediate( .{ .v_, .cvtps2ph }, dst_reg, |