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| author | Jacob Young <jacobly0@users.noreply.github.com> | 2023-05-14 17:26:44 -0400 |
|---|---|---|
| committer | Jacob Young <jacobly0@users.noreply.github.com> | 2023-05-15 03:07:51 -0400 |
| commit | 037bf1a580fe24b427e0ee5f7aecfec7202c1bf3 (patch) | |
| tree | 55cceeebcb554e3ffba8b586a2c75200d0480d26 /src/arch | |
| parent | 6c6d8d67cfe14c50684c04a579c1e62bf287e8cb (diff) | |
| download | zig-037bf1a580fe24b427e0ee5f7aecfec7202c1bf3.tar.gz zig-037bf1a580fe24b427e0ee5f7aecfec7202c1bf3.zip | |
x86_64: enable integer vector registers
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86_64/CodeGen.zig | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index 80f537e046..51e86447dc 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -2261,11 +2261,11 @@ fn allocRegOrMemAdvanced(self: *Self, ty: Type, inst: ?Air.Inst.Index, reg_ok: b }, .Vector => switch (ty.childType().zigTypeTag()) { .Float => switch (ty.childType().floatBits(self.target.*)) { - 16, 32, 64 => if (self.hasFeature(.avx)) 32 else 16, - 80, 128 => break :need_mem, + 16, 32, 64, 128 => if (self.hasFeature(.avx)) 32 else 16, + 80 => break :need_mem, else => unreachable, }, - else => break :need_mem, + else => if (self.hasFeature(.avx)) 32 else 16, }, else => 8, })) { |