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| author | Jacob Young <jacobly0@users.noreply.github.com> | 2023-03-25 08:58:00 -0400 |
|---|---|---|
| committer | Jacob Young <jacobly0@users.noreply.github.com> | 2023-03-25 16:23:55 -0400 |
| commit | d064cf639f0f05f0f5dda84c228783c37db010b8 (patch) | |
| tree | c52cdd96e3198623a07dec5709bb9deeb16a7b1e /src/arch/x86_64/encoder.zig | |
| parent | 77300c02d65af81da6019995e4f1a156ef364df4 (diff) | |
| download | zig-d064cf639f0f05f0f5dda84c228783c37db010b8.tar.gz zig-d064cf639f0f05f0f5dda84c228783c37db010b8.zip | |
x86_64: implement 128-bit shifts
Diffstat (limited to 'src/arch/x86_64/encoder.zig')
| -rw-r--r-- | src/arch/x86_64/encoder.zig | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/src/arch/x86_64/encoder.zig b/src/arch/x86_64/encoder.zig index 9206923ece..05f66062ac 100644 --- a/src/arch/x86_64/encoder.zig +++ b/src/arch/x86_64/encoder.zig @@ -174,7 +174,7 @@ pub const Instruction = struct { .td => try encoder.imm64(inst.op1.mem.moffs.offset), else => { const mem_op = switch (encoding.op_en) { - .m, .mi, .m1, .mc, .mr => inst.op1, + .m, .mi, .m1, .mc, .mr, .mri, .mrc => inst.op1, .rm, .rmi => inst.op2, else => unreachable, }; @@ -182,7 +182,7 @@ pub const Instruction = struct { .reg => |reg| { const rm = switch (encoding.op_en) { .m, .mi, .m1, .mc => encoding.modRmExt(), - .mr => inst.op2.reg.lowEnc(), + .mr, .mri, .mrc => inst.op2.reg.lowEnc(), .rm, .rmi => inst.op1.reg.lowEnc(), else => unreachable, }; @@ -191,7 +191,7 @@ pub const Instruction = struct { .mem => |mem| { const op = switch (encoding.op_en) { .m, .mi, .m1, .mc => .none, - .mr => inst.op2, + .mr, .mri, .mrc => inst.op2, .rm, .rmi => inst.op1, else => unreachable, }; @@ -202,7 +202,7 @@ pub const Instruction = struct { switch (encoding.op_en) { .mi => try encodeImm(inst.op2.imm, encoding.op2, encoder), - .rmi => try encodeImm(inst.op3.imm, encoding.op3, encoder), + .rmi, .mri => try encodeImm(inst.op3.imm, encoding.op3, encoder), else => {}, } }, @@ -251,7 +251,7 @@ pub const Instruction = struct { else => unreachable, }; } else null, - .m, .mi, .m1, .mc, .mr => if (inst.op1.isSegmentRegister()) blk: { + .m, .mi, .m1, .mc, .mr, .mri, .mrc => if (inst.op1.isSegmentRegister()) blk: { break :blk switch (inst.op1) { .reg => |r| r, .mem => |m| m.base().?, @@ -275,13 +275,11 @@ pub const Instruction = struct { switch (op_en) { .np, .i, .zi, .fd, .td, .d => {}, - .o, .oi => { - rex.b = inst.op1.reg.isExtended(); - }, - .m, .mi, .m1, .mc, .mr, .rm, .rmi => { + .o, .oi => rex.b = inst.op1.reg.isExtended(), + .m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc => { const r_op = switch (op_en) { .rm, .rmi => inst.op1, - .mr => inst.op2, + .mr, .mri, .mrc => inst.op2, else => null, }; if (r_op) |op| { @@ -290,7 +288,7 @@ pub const Instruction = struct { const b_x_op = switch (op_en) { .rm, .rmi => inst.op2, - .m, .mi, .m1, .mc, .mr => inst.op1, + .m, .mi, .m1, .mc, .mr, .mri, .mrc => inst.op1, else => unreachable, }; switch (b_x_op) { |