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| author | Jacob Young <jacobly0@users.noreply.github.com> | 2024-02-22 23:51:35 +0100 |
|---|---|---|
| committer | Jacob Young <jacobly0@users.noreply.github.com> | 2024-02-22 23:51:53 +0100 |
| commit | dbfa3238fefee0c802fceb39c8605a0b21659bd3 (patch) | |
| tree | 7675a3d354c42e548041e058fbd545698089086c /src/arch/x86_64/CodeGen.zig | |
| parent | 83e66d301eede71800a9b5d72010ce63dbbac3fc (diff) | |
| download | zig-dbfa3238fefee0c802fceb39c8605a0b21659bd3.tar.gz zig-dbfa3238fefee0c802fceb39c8605a0b21659bd3.zip | |
Builder: fix float constants in llvm ir
Diffstat (limited to 'src/arch/x86_64/CodeGen.zig')
| -rw-r--r-- | src/arch/x86_64/CodeGen.zig | 54 |
1 files changed, 31 insertions, 23 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index 857b980aad..f9a291f40b 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -16683,36 +16683,44 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void { else => null, }; defer if (elem_lock) |lock| self.register_manager.unlockReg(lock); - const elem_reg = registerAlias( - try self.copyToTmpRegister(elem_ty, mat_elem_mcv), - elem_abi_size, - ); + const elem_extra_bits = self.regExtraBits(elem_ty); - if (elem_bit_off < elem_extra_bits) { - try self.truncateRegister(elem_ty, elem_reg); + { + const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv); + const temp_alias = registerAlias(temp_reg, elem_abi_size); + const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg); + defer self.register_manager.unlockReg(temp_lock); + + if (elem_bit_off < elem_extra_bits) { + try self.truncateRegister(elem_ty, temp_alias); + } + if (elem_bit_off > 0) try self.genShiftBinOpMir( + .{ ._l, .sh }, + elem_ty, + .{ .register = temp_alias }, + Type.u8, + .{ .immediate = elem_bit_off }, + ); + try self.genBinOpMir( + .{ ._, .@"or" }, + elem_ty, + .{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } }, + .{ .register = temp_alias }, + ); } - if (elem_bit_off > 0) try self.genShiftBinOpMir( - .{ ._l, .sh }, - elem_ty, - .{ .register = elem_reg }, - Type.u8, - .{ .immediate = elem_bit_off }, - ); - try self.genBinOpMir( - .{ ._, .@"or" }, - elem_ty, - .{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } }, - .{ .register = elem_reg }, - ); if (elem_bit_off > elem_extra_bits) { - const reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv); + const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv); + const temp_alias = registerAlias(temp_reg, elem_abi_size); + const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg); + defer self.register_manager.unlockReg(temp_lock); + if (elem_extra_bits > 0) { - try self.truncateRegister(elem_ty, registerAlias(reg, elem_abi_size)); + try self.truncateRegister(elem_ty, temp_alias); } try self.genShiftBinOpMir( .{ ._r, .sh }, elem_ty, - .{ .register = reg }, + .{ .register = temp_reg }, Type.u8, .{ .immediate = elem_abi_bits - elem_bit_off }, ); @@ -16723,7 +16731,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void { .index = frame_index, .off = elem_byte_off + @as(i32, @intCast(elem_abi_size)), } }, - .{ .register = reg }, + .{ .register = temp_alias }, ); } } |