diff options
| author | Jakub Konka <kubkon@jakubkonka.com> | 2021-12-23 20:51:48 +0100 |
|---|---|---|
| committer | Jakub Konka <kubkon@jakubkonka.com> | 2021-12-23 20:51:48 +0100 |
| commit | dba5df64eacfbcca9727fe8596b186defb30a753 (patch) | |
| tree | 00cdd4f4926243ef70e15a0c5dc06a916e65b281 /src/arch/x86_64/CodeGen.zig | |
| parent | c50bb2b80f3ccdc361a12034e7919f5288131c5e (diff) | |
| download | zig-dba5df64eacfbcca9727fe8596b186defb30a753.tar.gz zig-dba5df64eacfbcca9727fe8596b186defb30a753.zip | |
stage2: use lowerToRmEnc to lower two-operand imul
Fix mismatched register sizes in codegen.
Diffstat (limited to 'src/arch/x86_64/CodeGen.zig')
| -rw-r--r-- | src/arch/x86_64/CodeGen.zig | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index 65bd3b857c..08a926216c 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -1717,7 +1717,7 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) ! _ = try self.addInst(.{ .tag = .imul_complex, .ops = (Mir.Ops{ - .reg1 = dst_reg, + .reg1 = registerAlias(dst_reg, @divExact(src_reg.size(), 8)), .reg2 = src_reg, }).encode(), .data = undefined, @@ -1766,7 +1766,7 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) ! _ = try self.addInst(.{ .tag = .imul_complex, .ops = (Mir.Ops{ - .reg1 = dst_reg, + .reg1 = registerAlias(dst_reg, @divExact(src_reg.size(), 8)), .reg2 = src_reg, }).encode(), .data = undefined, |