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| author | Jacob Young <jacobly0@users.noreply.github.com> | 2024-06-16 12:43:18 -0400 |
|---|---|---|
| committer | Jacob Young <jacobly0@users.noreply.github.com> | 2024-06-16 14:59:56 -0400 |
| commit | 96501d338550f47671692c669cb76eb99513a8da (patch) | |
| tree | 61385f8edbd3e94c32befb476e4340a17b205ec0 /src/arch/x86_64/CodeGen.zig | |
| parent | 17f14e1d65b59ebb1a8b5b617cc31fb2614f0c6a (diff) | |
| download | zig-96501d338550f47671692c669cb76eb99513a8da.tar.gz zig-96501d338550f47671692c669cb76eb99513a8da.zip | |
x86_64: get encoder tests passing again
Diffstat (limited to 'src/arch/x86_64/CodeGen.zig')
| -rw-r--r-- | src/arch/x86_64/CodeGen.zig | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index cc6e014080..b733f2b245 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -14529,6 +14529,7 @@ fn moveStrategy(self: *Self, ty: Type, class: Register.Class, aligned: bool) !Mo else => {}, }, }, + .ip => {}, } return self.fail("TODO moveStrategy for {}", .{ty.fmt(mod)}); } @@ -14685,6 +14686,7 @@ fn genSetReg( else => unreachable, }, .segment, .x87, .mmx, .sse => try self.genSetReg(dst_reg, ty, try self.genTypedValue(try mod.undefValue(ty)), opts), + .ip => unreachable, }, .eflags => |cc| try self.asmSetccRegister(cc, dst_reg.to8()), .immediate => |imm| { @@ -14722,7 +14724,7 @@ fn genSetReg( registerAlias(dst_reg, abi_size), src_reg, ), - .x87, .mmx => unreachable, + .x87, .mmx, .ip => unreachable, .sse => try self.asmRegisterRegister( switch (abi_size) { 1...4 => if (self.hasFeature(.avx)) .{ .v_d, .mov } else .{ ._d, .mov }, @@ -14738,7 +14740,7 @@ fn genSetReg( dst_reg, switch (src_reg.class()) { .general_purpose, .segment => registerAlias(src_reg, abi_size), - .x87, .mmx => unreachable, + .x87, .mmx, .ip => unreachable, .sse => try self.copyToTmpRegister(ty, src_mcv), }, ), @@ -14753,7 +14755,7 @@ fn genSetReg( }, else => unreachable, }, - .mmx, .sse => unreachable, + .mmx, .sse, .ip => unreachable, }, .mmx => unreachable, .sse => switch (src_reg.class()) { @@ -14772,7 +14774,7 @@ fn genSetReg( .{ .register = try self.copyToTmpRegister(ty, src_mcv) }, opts, ), - .x87, .mmx => unreachable, + .x87, .mmx, .ip => unreachable, .sse => try self.asmRegisterRegister( @as(?Mir.Inst.FixedTag, switch (ty.scalarType(mod).zigTypeTag(mod)) { else => switch (abi_size) { @@ -14799,6 +14801,7 @@ fn genSetReg( registerAlias(src_reg, abi_size), ), }, + .ip => unreachable, }, .register_pair => |src_regs| try self.genSetReg(dst_reg, ty, .{ .register = src_regs[0] }, opts), .register_offset, @@ -14866,7 +14869,7 @@ fn genSetReg( }); return; }, - .segment, .mmx => unreachable, + .segment, .mmx, .ip => unreachable, .x87, .sse => {}, }, .load_direct => |sym_index| switch (dst_reg.class()) { @@ -14884,7 +14887,7 @@ fn genSetReg( }); return; }, - .segment, .mmx => unreachable, + .segment, .mmx, .ip => unreachable, .x87, .sse => {}, }, .load_got, .load_tlv => {}, @@ -15047,7 +15050,7 @@ fn genSetMem( }; const src_alias = registerAlias(src_reg, abi_size); const src_size: u32 = @intCast(switch (src_alias.class()) { - .general_purpose, .segment, .x87 => @divExact(src_alias.bitSize(), 8), + .general_purpose, .segment, .x87, .ip => @divExact(src_alias.bitSize(), 8), .mmx, .sse => abi_size, }); const src_align = Alignment.fromNonzeroByteUnits(math.ceilPowerOfTwoAssert(u32, src_size)); @@ -19077,6 +19080,14 @@ fn registerAlias(reg: Register, size_bytes: u32) Register { reg.to256() else unreachable, + .ip => if (size_bytes <= 2) + .ip + else if (size_bytes <= 4) + .eip + else if (size_bytes <= 8) + .rip + else + unreachable, }; } |