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authorJacob Young <jacobly0@users.noreply.github.com>2024-02-10 23:09:32 +0100
committerJacob Young <jacobly0@users.noreply.github.com>2024-02-12 05:25:07 +0100
commit9023ff04d0dff0c5eff761c5aa1f8611106767d6 (patch)
tree7080f7891be1dc6f5a5c75dabdb473c0031d956e /src/arch/x86_64/CodeGen.zig
parenta9f738e56b65c8c510da11ec864460f414d82c95 (diff)
downloadzig-9023ff04d0dff0c5eff761c5aa1f8611106767d6.tar.gz
zig-9023ff04d0dff0c5eff761c5aa1f8611106767d6.zip
x86_64: fix register clobber
Diffstat (limited to 'src/arch/x86_64/CodeGen.zig')
-rw-r--r--src/arch/x86_64/CodeGen.zig15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index a0a83ee7ab..776eb1c44c 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -3776,6 +3776,9 @@ fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
.Vector => return self.fail("TODO implement add/sub with overflow for Vector type", .{}),
.Int => {
try self.spillEflagsIfOccupied();
+ try self.spillRegisters(&.{ .rcx, .rdi, .rsi });
+ const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rcx, .rdi, .rsi });
+ defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
const partial_mcv = try self.genBinOp(null, switch (tag) {
.add_with_overflow => .add,
@@ -3839,8 +3842,10 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
.Vector => return self.fail("TODO implement shl with overflow for Vector type", .{}),
.Int => {
try self.spillEflagsIfOccupied();
+ try self.spillRegisters(&.{ .rcx, .rdi, .rsi });
+ const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rcx, .rdi, .rsi });
+ defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
- try self.register_manager.getReg(.rcx, null);
const lhs = try self.resolveInst(bin_op.lhs);
const rhs = try self.resolveInst(bin_op.rhs);
@@ -4296,8 +4301,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
};
try self.spillEflagsIfOccupied();
- try self.spillRegisters(&.{ .rax, .rcx, .rdx });
- const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rax, .rcx, .rdx });
+ try self.spillRegisters(&.{ .rax, .rcx, .rdx, .rdi, .rsi });
+ const reg_locks = self.register_manager.lockRegsAssumeUnused(5, .{ .rax, .rcx, .rdx, .rdi, .rsi });
defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
const cc: Condition = switch (dst_info.signedness) {
@@ -8273,8 +8278,8 @@ fn genShiftBinOp(
assert(rhs_ty.abiSize(mod) == 1);
try self.register_manager.getReg(.rcx, null);
- const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);
- defer self.register_manager.unlockReg(rcx_lock);
+ const rcx_lock = self.register_manager.lockReg(.rcx);
+ defer if (rcx_lock) |lock| self.register_manager.unlockReg(lock);
const lhs_lock = switch (lhs_mcv) {
.register => |reg| self.register_manager.lockReg(reg),