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| author | Jakub Konka <kubkon@jakubkonka.com> | 2021-12-20 19:38:15 +0100 |
|---|---|---|
| committer | Jakub Konka <kubkon@jakubkonka.com> | 2021-12-20 23:29:41 +0100 |
| commit | 5156ccd552fa6d0959c8349cbbe176099ac4c356 (patch) | |
| tree | 62a76e97732ce29f9c46b460859b134c0bdc47ce /src/arch/x86_64/CodeGen.zig | |
| parent | 71c5eebd32d44ca01fedcb48674c5e7185f10289 (diff) | |
| download | zig-5156ccd552fa6d0959c8349cbbe176099ac4c356.tar.gz zig-5156ccd552fa6d0959c8349cbbe176099ac4c356.zip | |
stage2: merge MOV back with arith instructions
* turns out MOV and other arithmetic instructions such as ADD can
naturally share the same lowering codepath (for the same variants)
* there are variants that are specific to ADD, or MOV which will be
implemented as standalone MIR tags
* tweak Isel tests to generate corresponding test cases for all
arithmetic instructions in comptime
Diffstat (limited to 'src/arch/x86_64/CodeGen.zig')
| -rw-r--r-- | src/arch/x86_64/CodeGen.zig | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index 66bf43fb29..2660a02ca3 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -1608,18 +1608,18 @@ fn genBinMathOpMir( _ = try self.addInst(.{ .tag = mir_tag, .ops = (Mir.Ops{ - .reg1 = src_reg, - .reg2 = dst_reg, - .flags = 0b11, + .reg1 = registerAlias(dst_reg, @divExact(src_reg.size(), 8)), + .reg2 = src_reg, }).encode(), .data = undefined, }); }, .immediate => |imm| { + // TODO I am not quite sure why we need to set the size of the register here... _ = try self.addInst(.{ .tag = mir_tag, .ops = (Mir.Ops{ - .reg1 = dst_reg, + .reg1 = registerAlias(dst_reg, 4), }).encode(), .data = .{ .imm = @intCast(i32, imm) }, }); @@ -1637,7 +1637,7 @@ fn genBinMathOpMir( .tag = mir_tag, .ops = (Mir.Ops{ .reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)), - .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)), + .reg2 = .rbp, .flags = 0b01, }).encode(), .data = .{ .imm = -@intCast(i32, adj_off) }, @@ -1667,8 +1667,8 @@ fn genBinMathOpMir( _ = try self.addInst(.{ .tag = mir_tag, .ops = (Mir.Ops{ - .reg1 = registerAlias(src_reg, @intCast(u32, abi_size)), - .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)), + .reg1 = .rbp, + .reg2 = registerAlias(src_reg, @intCast(u32, abi_size)), .flags = 0b10, }).encode(), .data = .{ .imm = -@intCast(i32, adj_off) }, @@ -2924,6 +2924,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void } if (x <= math.maxInt(i32)) { // Next best case: if we set the lower four bytes, the upper four will be zeroed. + // TODO I am not quite sure why we need to set the size of the register here... _ = try self.addInst(.{ .tag = .mov, .ops = (Mir.Ops{ |