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| author | Andrew Kelley <andrew@ziglang.org> | 2022-05-04 19:11:02 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2022-05-04 19:11:02 -0700 |
| commit | 0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e (patch) | |
| tree | 9d6b8e844ab56425202e44c1be70260a099f203b /src/ThreadPool.zig | |
| parent | af7e945a7dc00a2a5055d9770b9ecda253d64a8e (diff) | |
| download | zig-0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e.tar.gz zig-0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e.zip | |
stage2: change max int align from 8 to 16 for more ISAs
These targets now have a similar disagreement with LLVM about the
alignment of 128-bit integers as x86_64:
* riscv64
* powerpc64
* powerpc64le
* mips64
* mips64el
* sparcv9
See #2987
Diffstat (limited to 'src/ThreadPool.zig')
0 files changed, 0 insertions, 0 deletions