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| author | Andrew Kelley <andrew@ziglang.org> | 2021-06-15 11:39:53 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2021-06-15 17:12:22 -0400 |
| commit | 90c73d8768bd51c84a5bf3d589d31abce6d93d37 (patch) | |
| tree | 3a8cd89a878209178a2c8561d15ef33cb6fb118e /src/Sema.zig | |
| parent | 515d6430c0298daf304e48b46e6b43802bbfdab4 (diff) | |
| download | zig-90c73d8768bd51c84a5bf3d589d31abce6d93d37.tar.gz zig-90c73d8768bd51c84a5bf3d589d31abce6d93d37.zip | |
fix RISC-V assembly CPU features
Previously, Zig did not properly communicate the target CPU features for
RISC-V to clang assembler, because Clang has a different way to pass CPU
features for C code and for assembly code. This commit makes Zig pass a
RISC-V -march flag in order to communicate CPU features to Clang when
compiling assembly files.
Diffstat (limited to 'src/Sema.zig')
0 files changed, 0 insertions, 0 deletions