stage2: implement `@setAlignStack` and 128-bit cmpxchg

 * test runner is improved to respect `error.SkipZigTest`
 * start code is improved to `@setAlignStack(16)` before calling main()
 * the newly passing behavior test has a workaround for the fact that
   stage2 cannot yet call `std.Target.x86.featureSetHas()` at comptime.
   This is blocking on comptime closures. The workaround is that there
   is a new decl `@import("builtin").stage2_x86_cx16` which is a `bool`.
 * Implement `@setAlignStack`. This language feature should be re-evaluated
   at some point - I'll file an issue for it.
 * LLVM backend: apply/remove the cold attribute and noinline attribute
   where appropriate.
 * LLVM backend: loads and stores are properly annotated with alignment
   and volatile attributes.
 * LLVM backend: allocas are properly annotated with alignment.
 * Type: fix integers reporting wrong alignment for 256-bit integers and
   beyond. Once you get to 16 byte aligned, there is no further
   alignment for larger integers.

1 files changed, 5 insertions, 0 deletions

diff --git a/src/Compilation.zig b/src/Compilation.zig
index cc72275293..8edbb2dd73 100644
--- a/src/Compilation.zig
+++ b/src/Compilation.zig
@@ -3714,6 +3714,8 @@ pub fn generateBuiltinZigSource(comp: *Compilation, allocator: *Allocator) Alloc
     const target = comp.getTarget();
     const generic_arch_name = target.cpu.arch.genericName();
     const use_stage1 = build_options.is_stage1 and comp.bin_file.options.use_stage1;
+    const stage2_x86_cx16 = target.cpu.arch == .x86_64 and
+        std.Target.x86.featureSetHas(target.cpu.features, .cx16);
 
     @setEvalBranchQuota(4000);
     try buffer.writer().print(
@@ -3725,6 +3727,8 @@ pub fn generateBuiltinZigSource(comp: *Compilation, allocator: *Allocator) Alloc
         \\pub const zig_is_stage2 = {};
         \\/// Temporary until self-hosted supports the `cpu.arch` value.
         \\pub const stage2_arch: std.Target.Cpu.Arch = .{};
+        \\/// Temporary until self-hosted can call `std.Target.x86.featureSetHas` at comptime.
+        \\pub const stage2_x86_cx16 = {};
         \\
         \\pub const output_mode = std.builtin.OutputMode.{};
         \\pub const link_mode = std.builtin.LinkMode.{};
@@ -3740,6 +3744,7 @@ pub fn generateBuiltinZigSource(comp: *Compilation, allocator: *Allocator) Alloc
         build_options.version,
         !use_stage1,
         std.zig.fmtId(@tagName(target.cpu.arch)),
+        stage2_x86_cx16,
         std.zig.fmtId(@tagName(comp.bin_file.options.output_mode)),
         std.zig.fmtId(@tagName(comp.bin_file.options.link_mode)),
         comp.bin_file.options.is_test,