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| author | Andrew Kelley <andrew@ziglang.org> | 2019-03-18 13:47:59 -0400 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2019-03-18 13:47:59 -0400 |
| commit | 7dfbeca13eca48a506bbeba6ce7a18b2a8d25ce1 (patch) | |
| tree | bfe391827fec58195e61a682b5a1da4e7111a67f /libc/include/riscv64-linux-gnu | |
| parent | 6acabd6b577ac63274b31bd1b2ae22cc75ab2c7a (diff) | |
| download | zig-7dfbeca13eca48a506bbeba6ce7a18b2a8d25ce1.tar.gz zig-7dfbeca13eca48a506bbeba6ce7a18b2a8d25ce1.zip | |
libc: separate linux headers from musl/glibc
Diffstat (limited to 'libc/include/riscv64-linux-gnu')
| -rw-r--r-- | libc/include/riscv64-linux-gnu/asm/unistd.h | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/libc/include/riscv64-linux-gnu/asm/unistd.h b/libc/include/riscv64-linux-gnu/asm/unistd.h deleted file mode 100644 index 1f3bd3ebbb..0000000000 --- a/libc/include/riscv64-linux-gnu/asm/unistd.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifdef __LP64__ -#define __ARCH_WANT_NEW_STAT -#endif /* __LP64__ */ - -#include <asm-generic/unistd.h> - -/* - * Allows the instruction cache to be flushed from userspace. Despite RISC-V - * having a direct 'fence.i' instruction available to userspace (which we - * can't trap!), that's not actually viable when running on Linux because the - * kernel might schedule a process on another hart. There is no way for - * userspace to handle this without invoking the kernel (as it doesn't know the - * thread->hart mappings), so we've defined a RISC-V specific system call to - * flush the instruction cache. - * - * __NR_riscv_flush_icache is defined to flush the instruction cache over an - * address range, with the flush applying to either all threads or just the - * caller. We don't currently do anything with the address range, that's just - * in there for forwards compatibility. - */ -#ifndef __NR_riscv_flush_icache -#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) -#endif -__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) |