Merge pull request #12001 from ziglang/llvm14

Upgrade to LLVM 14
author: Andrew Kelley <andrew@ziglang.org> 2022-07-10 03:06:05 -0400
committer: GitHub <noreply@github.com> 2022-07-10 03:06:05 -0400
commit: b88151e0e1553607cbebc197e1111ec4bf53a595 (patch)
tree: cd4f57feae521500fe4eb99a98a798241256d341 /lib/std
parent: 3f11d1d56d9747de974b00eab1c880bea7972c01 (diff)
parent: f9bf4889264aee387639bb8a35fdf594236b1283 (diff)
download: zig-b88151e0e1553607cbebc197e1111ec4bf53a595.tar.gz
zig-b88151e0e1553607cbebc197e1111ec4bf53a595.zip
20 files changed, 1850 insertions, 371 deletions
diff --git a/lib/std/fmt.zig b/lib/std/fmt.zig
index 86f3cebfec..90e70a7c41 100644
--- a/lib/std/fmt.zig
+++ b/lib/std/fmt.zig
@@ -2284,6 +2284,10 @@ test "float.hexadecimal.precision" {
 }
 
 test "float.decimal" {
+    if (builtin.zig_backend == .stage1 and builtin.os.tag == .windows) {
+        // https://github.com/ziglang/zig/issues/12063
+        return error.SkipZigTest;
+    }
     try expectFmt("f64: 152314000000000000000000000000", "f64: {d}", .{@as(f64, 1.52314e+29)});
     try expectFmt("f32: 0", "f32: {d}", .{@as(f32, 0.0)});
     try expectFmt("f32: 0", "f32: {d:.0}", .{@as(f32, 0.0)});
@@ -2307,6 +2311,10 @@ test "float.decimal" {
 }
 
 test "float.libc.sanity" {
+    if (builtin.zig_backend == .stage1 and builtin.os.tag == .windows) {
+        // https://github.com/ziglang/zig/issues/12063
+        return error.SkipZigTest;
+    }
     try expectFmt("f64: 0.00001", "f64: {d:.5}", .{@as(f64, @bitCast(f32, @as(u32, 916964781)))});
     try expectFmt("f64: 0.00001", "f64: {d:.5}", .{@as(f64, @bitCast(f32, @as(u32, 925353389)))});
     try expectFmt("f64: 0.10000", "f64: {d:.5}", .{@as(f64, @bitCast(f32, @as(u32, 1036831278)))});
@@ -2623,6 +2631,12 @@ test "vector" {
         return error.SkipZigTest;
     }
 
+    if (builtin.zig_backend == .stage1) {
+        // Regressed in LLVM 14:
+        // https://github.com/llvm/llvm-project/issues/55522
+        return error.SkipZigTest;
+    }
+
     const vbool: @Vector(4, bool) = [_]bool{ true, false, true, false };
     const vi64: @Vector(4, i64) = [_]i64{ -2, -1, 0, 1 };
     const vu64: @Vector(4, u64) = [_]u64{ 1000, 2000, 3000, 4000 };
diff --git a/lib/std/fmt/parse_float.zig b/lib/std/fmt/parse_float.zig
index 3013ca7865..2f30c30f23 100644
--- a/lib/std/fmt/parse_float.zig
+++ b/lib/std/fmt/parse_float.zig
@@ -1,6 +1,7 @@
 pub const parseFloat = @import("parse_float/parse_float.zig").parseFloat;
 pub const ParseFloatError = @import("parse_float/parse_float.zig").ParseFloatError;
 
+const builtin = @import("builtin");
 const std = @import("std");
 const math = std.math;
 const testing = std.testing;
@@ -14,8 +15,6 @@ const epsilon = 1e-7;
 
 test "fmt.parseFloat" {
     inline for ([_]type{ f16, f32, f64, f128 }) |T| {
-        const Z = std.meta.Int(.unsigned, @typeInfo(T).Float.bits);
-
         try testing.expectError(error.InvalidCharacter, parseFloat(T, ""));
         try testing.expectError(error.InvalidCharacter, parseFloat(T, "   1"));
         try testing.expectError(error.InvalidCharacter, parseFloat(T, "1abc"));
@@ -40,10 +39,6 @@ test "fmt.parseFloat" {
         try expectEqual(try parseFloat(T, "1e-5000"), 0);
         try expectEqual(try parseFloat(T, "1e+5000"), std.math.inf(T));
 
-        try expectEqual(@bitCast(Z, try parseFloat(T, "nAn")), @bitCast(Z, std.math.nan(T)));
-        try expectEqual(try parseFloat(T, "inF"), std.math.inf(T));
-        try expectEqual(try parseFloat(T, "-INF"), -std.math.inf(T));
-
         try expectEqual(try parseFloat(T, "0.4e0066999999999999999999999999999999999999999999999999999"), std.math.inf(T));
         try expect(approxEqAbs(T, try parseFloat(T, "0_1_2_3_4_5_6.7_8_9_0_0_0e0_0_1_0"), @as(T, 123456.789000e10), epsilon));
 
@@ -74,6 +69,23 @@ test "fmt.parseFloat" {
     }
 }
 
+test "fmt.parseFloat nan and inf" {
+    if ((builtin.zig_backend == .stage1 or builtin.zig_backend == .stage2_llvm) and
+        builtin.cpu.arch == .aarch64)
+    {
+        // https://github.com/ziglang/zig/issues/12027
+        return error.SkipZigTest;
+    }
+
+    inline for ([_]type{ f16, f32, f64, f128 }) |T| {
+        const Z = std.meta.Int(.unsigned, @typeInfo(T).Float.bits);
+
+        try expectEqual(@bitCast(Z, try parseFloat(T, "nAn")), @bitCast(Z, std.math.nan(T)));
+        try expectEqual(try parseFloat(T, "inF"), std.math.inf(T));
+        try expectEqual(try parseFloat(T, "-INF"), -std.math.inf(T));
+    }
+}
+
 test "fmt.parseFloat #11169" {
     try expectEqual(try parseFloat(f128, "9007199254740993.0"), 9007199254740993.0);
 }
diff --git a/lib/std/leb128.zig b/lib/std/leb128.zig
index 470bdc85ed..b18ca9fab0 100644
--- a/lib/std/leb128.zig
+++ b/lib/std/leb128.zig
@@ -1,3 +1,4 @@
+const builtin = @import("builtin");
 const std = @import("std");
 const testing = std.testing;
 
@@ -346,6 +347,13 @@ fn test_write_leb128(value: anytype) !void {
 }
 
 test "serialize unsigned LEB128" {
+    if ((builtin.zig_backend == .stage1 or builtin.zig_backend == .stage2_llvm) and
+        builtin.cpu.arch == .riscv64)
+    {
+        // https://github.com/ziglang/zig/issues/12031
+        return error.SkipZigTest;
+    }
+
     const max_bits = 18;
 
     comptime var t = 0;
@@ -360,6 +368,13 @@ test "serialize unsigned LEB128" {
 }
 
 test "serialize signed LEB128" {
+    if ((builtin.zig_backend == .stage1 or builtin.zig_backend == .stage2_llvm) and
+        builtin.cpu.arch == .riscv64)
+    {
+        // https://github.com/ziglang/zig/issues/12031
+        return error.SkipZigTest;
+    }
+
     // explicitly test i0 because starting `t` at 0
     // will break the while loop
     try test_write_leb128(@as(i0, 0));
diff --git a/lib/std/math.zig b/lib/std/math.zig
index 94a7cc7e01..0487ef2d3c 100644
--- a/lib/std/math.zig
+++ b/lib/std/math.zig
@@ -1647,6 +1647,10 @@ fn testSign() !void {
 }
 
 test "sign" {
+    if (builtin.zig_backend == .stage1 or builtin.zig_backend == .stage2_llvm) {
+        // https://github.com/ziglang/zig/issues/12012
+        return error.SkipZigTest;
+    }
     try testSign();
     comptime try testSign();
 }
diff --git a/lib/std/mem.zig b/lib/std/mem.zig
index f54610f060..13322c9bee 100644
--- a/lib/std/mem.zig
+++ b/lib/std/mem.zig
@@ -331,6 +331,12 @@ pub fn zeroes(comptime T: type) T {
 }
 
 test "zeroes" {
+    if (builtin.zig_backend == .stage1 or builtin.zig_backend == .stage2_llvm) {
+        // Regressed in LLVM 14:
+        // https://github.com/llvm/llvm-project/issues/55522
+        return error.SkipZigTest;
+    }
+
     const C_struct = extern struct {
         x: u32,
         y: u32,
@@ -370,9 +376,9 @@ test "zeroes" {
         },
 
         array: [2]u32,
-        vector_u32: meta.Vector(2, u32),
-        vector_f32: meta.Vector(2, f32),
-        vector_bool: meta.Vector(2, bool),
+        vector_u32: @Vector(2, u32),
+        vector_f32: @Vector(2, f32),
+        vector_bool: @Vector(2, bool),
         optional_int: ?u8,
         empty: void,
         sentinel: [3:0]u8,
diff --git a/lib/std/simd.zig b/lib/std/simd.zig
index a30622aef6..1a71bd7069 100644
--- a/lib/std/simd.zig
+++ b/lib/std/simd.zig
@@ -160,6 +160,12 @@ pub fn extract(
 }
 
 test "vector patterns" {
+    if ((builtin.zig_backend == .stage1 or builtin.zig_backend == .stage2_llvm) and
+        builtin.cpu.arch == .aarch64)
+    {
+        // https://github.com/ziglang/zig/issues/12012
+        return error.SkipZigTest;
+    }
     const base = @Vector(4, u32){ 10, 20, 30, 40 };
     const other_base = @Vector(4, u32){ 55, 66, 77, 88 };
 
@@ -382,6 +388,12 @@ test "vector prefix scan" {
         return error.SkipZigTest;
     }
 
+    if (builtin.zig_backend == .stage1 or builtin.zig_backend == .stage2_llvm) {
+        // Regressed in LLVM 14:
+        // https://github.com/llvm/llvm-project/issues/55522
+        return error.SkipZigTest;
+    }
+
     const int_base = @Vector(4, i32){ 11, 23, 9, -21 };
     const float_base = @Vector(4, f32){ 2, 0.5, -10, 6.54321 };
     const bool_base = @Vector(4, bool){ true, false, true, false };
diff --git a/lib/std/target.zig b/lib/std/target.zig
index eae227fc37..f026b0da21 100644
--- a/lib/std/target.zig
+++ b/lib/std/target.zig
@@ -444,6 +444,7 @@ pub const Target = struct {
     pub const arm = @import("target/arm.zig");
     pub const avr = @import("target/avr.zig");
     pub const bpf = @import("target/bpf.zig");
+    pub const csky = @import("target/csky.zig");
     pub const hexagon = @import("target/hexagon.zig");
     pub const mips = @import("target/mips.zig");
     pub const msp430 = @import("target/msp430.zig");
@@ -804,6 +805,8 @@ pub const Target = struct {
             hsail64,
             spir,
             spir64,
+            spirv32,
+            spirv64,
             kalimba,
             shave,
             lanai,
@@ -815,8 +818,6 @@ pub const Target = struct {
             // Stage1 currently assumes that architectures above this comment
             // map one-to-one with the ZigLLVM_ArchType enum.
             spu_2,
-            spirv32,
-            spirv64,
 
             pub fn isX86(arch: Arch) bool {
                 return switch (arch) {
@@ -1287,7 +1288,7 @@ pub const Target = struct {
                     .sparc, .sparcel => &sparc.cpu.generic,
                     .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
                     .s390x => &systemz.cpu.generic,
-                    .i386 => &x86.cpu._i386,
+                    .i386 => &x86.cpu.i386,
                     .x86_64 => &x86.cpu.x86_64,
                     .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
                     .ve => &ve.cpu.generic,
diff --git a/lib/std/target/aarch64.zig b/lib/std/target/aarch64.zig
index 53363ee982..5a93276505 100644
--- a/lib/std/target/aarch64.zig
+++ b/lib/std/target/aarch64.zig
@@ -5,17 +5,18 @@ const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
+    a510,
     a65,
+    a710,
     a76,
+    a78,
+    a78c,
     aes,
     aggressive_fma,
     alternate_sextload_cvt_f32_pattern,
     altnzcv,
     am,
     amvs,
-    apple_a12,
-    apple_a13,
-    apple_a7,
     arith_bcc_fusion,
     arith_cbz_fusion,
     balance_fp_ops,
@@ -37,7 +38,6 @@ pub const Feature = enum {
     cmp_bcc_fusion,
     complxnum,
     contextidr_el2,
-    cortex_a78c,
     cortex_r82,
     crc,
     crypto,
@@ -46,12 +46,14 @@ pub const Feature = enum {
     dit,
     dotprod,
     ecv,
+    el2vmsa,
+    el3,
     ete,
     exynos_cheap_as_move,
-    exynos_m4,
     f32mm,
     f64mm,
     fgt,
+    fix_cortex_a53_835769,
     flagm,
     force_32bit_jump_tables,
     fp16fml,
@@ -67,20 +69,20 @@ pub const Feature = enum {
     harden_sls_blr,
     harden_sls_nocomdat,
     harden_sls_retbr,
+    hbc,
     hcx,
     i8mm,
     jsconv,
     lor,
     ls64,
     lse,
+    lse2,
     lsl_fast,
+    mops,
     mpam,
     mte,
     neon,
-    neoverse_e1,
-    neoverse_n1,
-    neoverse_n2,
-    neoverse_v1,
+    no_bti_at_return_twice,
     no_neg_immediates,
     no_zcz_fp,
     nv,
@@ -89,7 +91,6 @@ pub const Feature = enum {
     pan_rwv,
     pauth,
     perfmon,
-    pmu,
     predictable_select_expensive,
     predres,
     rand,
@@ -138,6 +139,7 @@ pub const Feature = enum {
     spe_eef,
     specrestrict,
     ssbs,
+    streaming_sve,
     strict_align,
     sve,
     sve2,
@@ -157,6 +159,7 @@ pub const Feature = enum {
     use_experimental_zeroing_pseudos,
     use_postra_scheduler,
     use_reciprocal_square_root,
+    use_scalar_inc_vl,
     v8_1a,
     v8_2a,
     v8_3a,
@@ -164,8 +167,13 @@ pub const Feature = enum {
     v8_5a,
     v8_6a,
     v8_7a,
+    v8_8a,
     v8a,
     v8r,
+    v9_1a,
+    v9_2a,
+    v9_3a,
+    v9a,
     vh,
     wfxt,
     xs,
@@ -185,32 +193,55 @@ pub const all_features = blk: {
     const len = @typeInfo(Feature).Enum.fields.len;
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
+    result[@enumToInt(Feature.a510)] = .{
+        .llvm_name = "a510",
+        .description = "Cortex-A510 ARM processors",
+        .dependencies = featureSet(&[_]Feature{
+            .fuse_aes,
+            .use_postra_scheduler,
+        }),
+    };
     result[@enumToInt(Feature.a65)] = .{
         .llvm_name = "a65",
         .description = "Cortex-A65 ARM processors",
         .dependencies = featureSet(&[_]Feature{
-            .crypto,
-            .dotprod,
-            .fullfp16,
             .fuse_address,
             .fuse_aes,
             .fuse_literals,
-            .rcpc,
-            .ssbs,
-            .v8_2a,
+        }),
+    };
+    result[@enumToInt(Feature.a710)] = .{
+        .llvm_name = "a710",
+        .description = "Cortex-A710 ARM processors",
+        .dependencies = featureSet(&[_]Feature{
+            .cmp_bcc_fusion,
+            .fuse_aes,
+            .use_postra_scheduler,
         }),
     };
     result[@enumToInt(Feature.a76)] = .{
         .llvm_name = "a76",
         .description = "Cortex-A76 ARM processors",
         .dependencies = featureSet(&[_]Feature{
-            .crypto,
-            .dotprod,
-            .fullfp16,
             .fuse_aes,
-            .rcpc,
-            .ssbs,
-            .v8_2a,
+        }),
+    };
+    result[@enumToInt(Feature.a78)] = .{
+        .llvm_name = "a78",
+        .description = "Cortex-A78 ARM processors",
+        .dependencies = featureSet(&[_]Feature{
+            .cmp_bcc_fusion,
+            .fuse_aes,
+            .use_postra_scheduler,
+        }),
+    };
+    result[@enumToInt(Feature.a78c)] = .{
+        .llvm_name = "a78c",
+        .description = "Cortex-A78C ARM processors",
+        .dependencies = featureSet(&[_]Feature{
+            .cmp_bcc_fusion,
+            .fuse_aes,
+            .use_postra_scheduler,
         }),
     };
     result[@enumToInt(Feature.aes)] = .{
@@ -247,60 +278,6 @@ pub const all_features = blk: {
             .am,
         }),
     };
-    result[@enumToInt(Feature.apple_a12)] = .{
-        .llvm_name = "apple-a12",
-        .description = "Apple A12",
-        .dependencies = featureSet(&[_]Feature{
-            .alternate_sextload_cvt_f32_pattern,
-            .arith_bcc_fusion,
-            .arith_cbz_fusion,
-            .crypto,
-            .disable_latency_sched_heuristic,
-            .fullfp16,
-            .fuse_aes,
-            .fuse_crypto_eor,
-            .perfmon,
-            .v8_3a,
-            .zcm,
-            .zcz,
-        }),
-    };
-    result[@enumToInt(Feature.apple_a13)] = .{
-        .llvm_name = "apple-a13",
-        .description = "Apple A13",
-        .dependencies = featureSet(&[_]Feature{
-            .alternate_sextload_cvt_f32_pattern,
-            .arith_bcc_fusion,
-            .arith_cbz_fusion,
-            .crypto,
-            .disable_latency_sched_heuristic,
-            .fp16fml,
-            .fuse_aes,
-            .fuse_crypto_eor,
-            .perfmon,
-            .sha3,
-            .v8_4a,
-            .zcm,
-            .zcz,
-        }),
-    };
-    result[@enumToInt(Feature.apple_a7)] = .{
-        .llvm_name = "apple-a7",
-        .description = "Apple A7 (the CPU formerly known as Cyclone)",
-        .dependencies = featureSet(&[_]Feature{
-            .alternate_sextload_cvt_f32_pattern,
-            .arith_bcc_fusion,
-            .arith_cbz_fusion,
-            .crypto,
-            .disable_latency_sched_heuristic,
-            .fuse_aes,
-            .fuse_crypto_eor,
-            .perfmon,
-            .zcm,
-            .zcz,
-            .zcz_fp_workaround,
-        }),
-    };
     result[@enumToInt(Feature.arith_bcc_fusion)] = .{
         .llvm_name = "arith-bcc-fusion",
         .description = "CPU fuses arithmetic+bcc operations",
@@ -408,31 +385,11 @@ pub const all_features = blk: {
         .description = "Enable RW operand Context ID Register (EL2)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.cortex_a78c)] = .{
-        .llvm_name = "cortex-a78c",
-        .description = "Cortex-A78C ARM processors",
-        .dependencies = featureSet(&[_]Feature{
-            .cmp_bcc_fusion,
-            .crypto,
-            .dotprod,
-            .flagm,
-            .fp16fml,
-            .fuse_aes,
-            .pauth,
-            .perfmon,
-            .rcpc,
-            .spe,
-            .ssbs,
-            .use_postra_scheduler,
-            .v8_2a,
-        }),
-    };
     result[@enumToInt(Feature.cortex_r82)] = .{
         .llvm_name = "cortex-r82",
-        .description = "Cortex-R82 ARM Processors",
+        .description = "Cortex-R82 ARM processors",
         .dependencies = featureSet(&[_]Feature{
             .use_postra_scheduler,
-            .v8r,
         }),
     };
     result[@enumToInt(Feature.crc)] = .{
@@ -473,6 +430,16 @@ pub const all_features = blk: {
         .description = "Enable enhanced counter virtualization extension",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.el2vmsa)] = .{
+        .llvm_name = "el2vmsa",
+        .description = "Enable Exception Level 2 Virtual Memory System Architecture",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.el3)] = .{
+        .llvm_name = "el3",
+        .description = "Enable Exception Level 3",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.ete)] = .{
         .llvm_name = "ete",
         .description = "Enable Embedded Trace Extension",
@@ -487,29 +454,6 @@ pub const all_features = blk: {
             .custom_cheap_as_move,
         }),
     };
-    result[@enumToInt(Feature.exynos_m4)] = .{
-        .llvm_name = "exynosm4",
-        .description = "Samsung Exynos-M4 processors",
-        .dependencies = featureSet(&[_]Feature{
-            .arith_bcc_fusion,
-            .arith_cbz_fusion,
-            .crypto,
-            .dotprod,
-            .exynos_cheap_as_move,
-            .force_32bit_jump_tables,
-            .fullfp16,
-            .fuse_address,
-            .fuse_aes,
-            .fuse_arith_logic,
-            .fuse_csel,
-            .fuse_literals,
-            .lsl_fast,
-            .perfmon,
-            .use_postra_scheduler,
-            .v8_2a,
-            .zcz,
-        }),
-    };
     result[@enumToInt(Feature.f32mm)] = .{
         .llvm_name = "f32mm",
         .description = "Enable Matrix Multiply FP32 Extension",
@@ -529,6 +473,11 @@ pub const all_features = blk: {
         .description = "Enable fine grained virtualization traps extension",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.fix_cortex_a53_835769)] = .{
+        .llvm_name = "fix-cortex-a53-835769",
+        .description = "Mitigate Cortex-A53 Erratum 835769",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.flagm)] = .{
         .llvm_name = "flagm",
         .description = "Enable v8.4-A Flag Manipulation Instructions",
@@ -608,6 +557,11 @@ pub const all_features = blk: {
         .description = "Harden against straight line speculation across RET and BR instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.hbc)] = .{
+        .llvm_name = "hbc",
+        .description = "Enable Armv8.8-A Hinted Conditional Branches Extension",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.hcx)] = .{
         .llvm_name = "hcx",
         .description = "Enable Armv8.7-A HCRX_EL2 system register",
@@ -640,11 +594,21 @@ pub const all_features = blk: {
         .description = "Enable ARMv8.1 Large System Extension (LSE) atomic instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.lse2)] = .{
+        .llvm_name = "lse2",
+        .description = "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.lsl_fast)] = .{
         .llvm_name = "lsl-fast",
         .description = "CPU has a fastpath logical shift of up to 3 places",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.mops)] = .{
+        .llvm_name = "mops",
+        .description = "Enable Armv8.8-A memcpy and memset acceleration instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.mpam)] = .{
         .llvm_name = "mpam",
         .description = "Enable v8.4-A Memory system Partitioning and Monitoring extension",
@@ -662,68 +626,10 @@ pub const all_features = blk: {
             .fp_armv8,
         }),
     };
-    result[@enumToInt(Feature.neoverse_e1)] = .{
-        .llvm_name = "neoversee1",
-        .description = "Neoverse E1 ARM processors",
-        .dependencies = featureSet(&[_]Feature{
-            .crypto,
-            .dotprod,
-            .fullfp16,
-            .fuse_aes,
-            .rcpc,
-            .ssbs,
-            .use_postra_scheduler,
-            .v8_2a,
-        }),
-    };
-    result[@enumToInt(Feature.neoverse_n1)] = .{
-        .llvm_name = "neoversen1",
-        .description = "Neoverse N1 ARM processors",
-        .dependencies = featureSet(&[_]Feature{
-            .crypto,
-            .dotprod,
-            .fullfp16,
-            .fuse_aes,
-            .rcpc,
-            .spe,
-            .ssbs,
-            .use_postra_scheduler,
-            .v8_2a,
-        }),
-    };
-    result[@enumToInt(Feature.neoverse_n2)] = .{
-        .llvm_name = "neoversen2",
-        .description = "Neoverse N2 ARM processors",
-        .dependencies = featureSet(&[_]Feature{
-            .bf16,
-            .crypto,
-            .ete,
-            .fuse_aes,
-            .i8mm,
-            .mte,
-            .sve2_bitperm,
-            .use_postra_scheduler,
-            .v8_5a,
-        }),
-    };
-    result[@enumToInt(Feature.neoverse_v1)] = .{
-        .llvm_name = "neoversev1",
-        .description = "Neoverse V1 ARM processors",
-        .dependencies = featureSet(&[_]Feature{
-            .bf16,
-            .ccdp,
-            .crypto,
-            .fp16fml,
-            .fuse_aes,
-            .i8mm,
-            .perfmon,
-            .rand,
-            .spe,
-            .ssbs,
-            .sve,
-            .use_postra_scheduler,
-            .v8_4a,
-        }),
+    result[@enumToInt(Feature.no_bti_at_return_twice)] = .{
+        .llvm_name = "no-bti-at-return-twice",
+        .description = "Don't place a BTI instruction after a return-twice",
+        .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.no_neg_immediates)] = .{
         .llvm_name = "no-neg-immediates",
@@ -767,11 +673,6 @@ pub const all_features = blk: {
         .description = "Enable ARMv8 PMUv3 Performance Monitors extension",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.pmu)] = .{
-        .llvm_name = "pmu",
-        .description = "Enable v8.4-A PMU extension",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@enumToInt(Feature.predictable_select_expensive)] = .{
         .llvm_name = "predictable-select-expensive",
         .description = "Prefer likely predicted branches over selects",
@@ -990,7 +891,7 @@ pub const all_features = blk: {
         .description = "Enable Scalable Matrix Extension (SME)",
         .dependencies = featureSet(&[_]Feature{
             .bf16,
-            .sve2,
+            .streaming_sve,
         }),
     };
     result[@enumToInt(Feature.sme_f64)] = .{
@@ -1027,6 +928,11 @@ pub const all_features = blk: {
         .description = "Enable Speculative Store Bypass Safe bit",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.streaming_sve)] = .{
+        .llvm_name = "streaming-sve",
+        .description = "Enable subset of SVE(2) instructions for Streaming SVE execution mode",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.strict_align)] = .{
         .llvm_name = "strict-align",
         .description = "Disallow all unaligned memory access",
@@ -1044,6 +950,7 @@ pub const all_features = blk: {
         .description = "Enable Scalable Vector Extension 2 (SVE2) instructions",
         .dependencies = featureSet(&[_]Feature{
             .sve,
+            .use_scalar_inc_vl,
         }),
     };
     result[@enumToInt(Feature.sve2_aes)] = .{
@@ -1137,6 +1044,11 @@ pub const all_features = blk: {
         .description = "Use the reciprocal square root approximation",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.use_scalar_inc_vl)] = .{
+        .llvm_name = "use-scalar-inc-vl",
+        .description = "Prefer inc/dec over add+cnt",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.v8_1a)] = .{
         .llvm_name = "v8.1a",
         .description = "Support ARM v8.1a instructions",
@@ -1181,9 +1093,9 @@ pub const all_features = blk: {
             .dit,
             .dotprod,
             .flagm,
+            .lse2,
             .mpam,
             .nv,
-            .pmu,
             .rcpc_immo,
             .sel2,
             .tlb_rmi,
@@ -1228,10 +1140,21 @@ pub const all_features = blk: {
             .xs,
         }),
     };
+    result[@enumToInt(Feature.v8_8a)] = .{
+        .llvm_name = "v8.8a",
+        .description = "Support ARM v8.8a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .hbc,
+            .mops,
+            .v8_7a,
+        }),
+    };
     result[@enumToInt(Feature.v8a)] = .{
-        .llvm_name = null,
-        .description = "Support ARM v8a instructions",
+        .llvm_name = "v8a",
+        .description = "Support ARM v8.0a instructions",
         .dependencies = featureSet(&[_]Feature{
+            .el2vmsa,
+            .el3,
             .neon,
         }),
     };
@@ -1247,27 +1170,51 @@ pub const all_features = blk: {
             .dit,
             .dotprod,
             .flagm,
-            .fp16fml,
             .jsconv,
             .lse,
             .pan_rwv,
             .pauth,
-            .perfmon,
-            .predres,
             .ras,
             .rcpc_immo,
             .rdm,
-            .sb,
             .sel2,
-            .sha3,
-            .sm4,
-            .specrestrict,
-            .ssbs,
             .tlb_rmi,
             .tracev8_4,
             .uaops,
         }),
     };
+    result[@enumToInt(Feature.v9_1a)] = .{
+        .llvm_name = "v9.1a",
+        .description = "Support ARM v9.1a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .v8_6a,
+            .v9a,
+        }),
+    };
+    result[@enumToInt(Feature.v9_2a)] = .{
+        .llvm_name = "v9.2a",
+        .description = "Support ARM v9.2a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .v8_7a,
+            .v9_1a,
+        }),
+    };
+    result[@enumToInt(Feature.v9_3a)] = .{
+        .llvm_name = "v9.3a",
+        .description = "Support ARM v9.3a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .v8_8a,
+            .v9_2a,
+        }),
+    };
+    result[@enumToInt(Feature.v9a)] = .{
+        .llvm_name = "v9a",
+        .description = "Support ARM v9a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .sve2,
+            .v8_5a,
+        }),
+    };
     result[@enumToInt(Feature.vh)] = .{
         .llvm_name = "vh",
         .description = "Enables ARM v8.1 Virtual Host extension",
@@ -1331,6 +1278,23 @@ pub const cpu = struct {
             .v8_2a,
         }),
     };
+    pub const ampere1 = CpuModel{
+        .name = "ampere1",
+        .llvm_name = "ampere1",
+        .features = featureSet(&[_]Feature{
+            .aggressive_fma,
+            .arith_bcc_fusion,
+            .cmp_bcc_fusion,
+            .fuse_address,
+            .fuse_aes,
+            .fuse_literals,
+            .lsl_fast,
+            .mte,
+            .perfmon,
+            .use_postra_scheduler,
+            .v8_6a,
+        }),
+    };
     pub const apple_a10 = CpuModel{
         .name = "apple_a10",
         .llvm_name = "apple-a10",
@@ -1347,6 +1311,7 @@ pub const cpu = struct {
             .pan,
             .perfmon,
             .rdm,
+            .v8a,
             .vh,
             .zcm,
             .zcz,
@@ -1374,14 +1339,37 @@ pub const cpu = struct {
         .name = "apple_a12",
         .llvm_name = "apple-a12",
         .features = featureSet(&[_]Feature{
-            .apple_a12,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fullfp16,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .v8_3a,
+            .zcm,
+            .zcz,
         }),
     };
     pub const apple_a13 = CpuModel{
         .name = "apple_a13",
         .llvm_name = "apple-a13",
         .features = featureSet(&[_]Feature{
-            .apple_a13,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fp16fml,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .sha3,
+            .v8_4a,
+            .zcm,
+            .zcz,
         }),
     };
     pub const apple_a14 = CpuModel{
@@ -1419,21 +1407,54 @@ pub const cpu = struct {
         .name = "apple_a7",
         .llvm_name = "apple-a7",
         .features = featureSet(&[_]Feature{
-            .apple_a7,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .v8a,
+            .zcm,
+            .zcz,
+            .zcz_fp_workaround,
         }),
     };
     pub const apple_a8 = CpuModel{
         .name = "apple_a8",
         .llvm_name = "apple-a8",
         .features = featureSet(&[_]Feature{
-            .apple_a7,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .v8a,
+            .zcm,
+            .zcz,
+            .zcz_fp_workaround,
         }),
     };
     pub const apple_a9 = CpuModel{
         .name = "apple_a9",
         .llvm_name = "apple-a9",
         .features = featureSet(&[_]Feature{
-            .apple_a7,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .v8a,
+            .zcm,
+            .zcz,
+            .zcz_fp_workaround,
         }),
     };
     pub const apple_latest = CpuModel{
@@ -1502,14 +1523,36 @@ pub const cpu = struct {
         .name = "apple_s4",
         .llvm_name = "apple-s4",
         .features = featureSet(&[_]Feature{
-            .apple_a12,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fullfp16,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .v8_3a,
+            .zcm,
+            .zcz,
         }),
     };
     pub const apple_s5 = CpuModel{
         .name = "apple_s5",
         .llvm_name = "apple-s5",
         .features = featureSet(&[_]Feature{
-            .apple_a12,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fullfp16,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .v8_3a,
+            .zcm,
+            .zcz,
         }),
     };
     pub const carmel = CpuModel{
@@ -1541,6 +1584,21 @@ pub const cpu = struct {
             .v8a,
         }),
     };
+    pub const cortex_a510 = CpuModel{
+        .name = "cortex_a510",
+        .llvm_name = "cortex-a510",
+        .features = featureSet(&[_]Feature{
+            .a510,
+            .bf16,
+            .ete,
+            .fp16fml,
+            .i8mm,
+            .mte,
+            .perfmon,
+            .sve2_bitperm,
+            .v9a,
+        }),
+    };
     pub const cortex_a53 = CpuModel{
         .name = "cortex_a53",
         .llvm_name = "cortex-a53",
@@ -1562,6 +1620,7 @@ pub const cpu = struct {
             .crypto,
             .dotprod,
             .fullfp16,
+            .fuse_address,
             .fuse_aes,
             .perfmon,
             .rcpc,
@@ -1590,6 +1649,12 @@ pub const cpu = struct {
         .llvm_name = "cortex-a65",
         .features = featureSet(&[_]Feature{
             .a65,
+            .crypto,
+            .dotprod,
+            .fullfp16,
+            .rcpc,
+            .ssbs,
+            .v8_2a,
         }),
     };
     pub const cortex_a65ae = CpuModel{
@@ -1597,6 +1662,27 @@ pub const cpu = struct {
         .llvm_name = "cortex-a65ae",
         .features = featureSet(&[_]Feature{
             .a65,
+            .crypto,
+            .dotprod,
+            .fullfp16,
+            .rcpc,
+            .ssbs,
+            .v8_2a,
+        }),
+    };
+    pub const cortex_a710 = CpuModel{
+        .name = "cortex_a710",
+        .llvm_name = "cortex-a710",
+        .features = featureSet(&[_]Feature{
+            .a710,
+            .bf16,
+            .ete,
+            .fp16fml,
+            .i8mm,
+            .mte,
+            .perfmon,
+            .sve2_bitperm,
+            .v9a,
         }),
     };
     pub const cortex_a72 = CpuModel{
@@ -1640,6 +1726,12 @@ pub const cpu = struct {
         .llvm_name = "cortex-a76",
         .features = featureSet(&[_]Feature{
             .a76,
+            .crypto,
+            .dotprod,
+            .fullfp16,
+            .rcpc,
+            .ssbs,
+            .v8_2a,
         }),
     };
     pub const cortex_a76ae = CpuModel{
@@ -1647,6 +1739,12 @@ pub const cpu = struct {
         .llvm_name = "cortex-a76ae",
         .features = featureSet(&[_]Feature{
             .a76,
+            .crypto,
+            .dotprod,
+            .fullfp16,
+            .rcpc,
+            .ssbs,
+            .v8_2a,
         }),
     };
     pub const cortex_a77 = CpuModel{
@@ -1659,6 +1757,7 @@ pub const cpu = struct {
             .fullfp16,
             .fuse_aes,
             .rcpc,
+            .ssbs,
             .v8_2a,
         }),
     };
@@ -1666,16 +1765,14 @@ pub const cpu = struct {
         .name = "cortex_a78",
         .llvm_name = "cortex-a78",
         .features = featureSet(&[_]Feature{
-            .cmp_bcc_fusion,
+            .a78,
             .crypto,
             .dotprod,
             .fullfp16,
-            .fuse_aes,
             .perfmon,
             .rcpc,
             .spe,
             .ssbs,
-            .use_postra_scheduler,
             .v8_2a,
         }),
     };
@@ -1683,7 +1780,17 @@ pub const cpu = struct {
         .name = "cortex_a78c",
         .llvm_name = "cortex-a78c",
         .features = featureSet(&[_]Feature{
-            .cortex_a78c,
+            .a78c,
+            .crypto,
+            .dotprod,
+            .flagm,
+            .fp16fml,
+            .pauth,
+            .perfmon,
+            .rcpc,
+            .spe,
+            .ssbs,
+            .v8_2a,
         }),
     };
     pub const cortex_r82 = CpuModel{
@@ -1691,6 +1798,13 @@ pub const cpu = struct {
         .llvm_name = "cortex-r82",
         .features = featureSet(&[_]Feature{
             .cortex_r82,
+            .fp16fml,
+            .perfmon,
+            .predres,
+            .sb,
+            .specrestrict,
+            .ssbs,
+            .v8r,
         }),
     };
     pub const cortex_x1 = CpuModel{
@@ -1705,15 +1819,62 @@ pub const cpu = struct {
             .perfmon,
             .rcpc,
             .spe,
+            .ssbs,
+            .use_postra_scheduler,
+            .v8_2a,
+        }),
+    };
+    pub const cortex_x1c = CpuModel{
+        .name = "cortex_x1c",
+        .llvm_name = "cortex-x1c",
+        .features = featureSet(&[_]Feature{
+            .cmp_bcc_fusion,
+            .crypto,
+            .dotprod,
+            .fullfp16,
+            .fuse_aes,
+            .pauth,
+            .perfmon,
+            .rcpc,
+            .spe,
+            .ssbs,
             .use_postra_scheduler,
             .v8_2a,
         }),
     };
+    pub const cortex_x2 = CpuModel{
+        .name = "cortex_x2",
+        .llvm_name = "cortex-x2",
+        .features = featureSet(&[_]Feature{
+            .bf16,
+            .cmp_bcc_fusion,
+            .ete,
+            .fp16fml,
+            .fuse_aes,
+            .i8mm,
+            .mte,
+            .perfmon,
+            .sve2_bitperm,
+            .use_postra_scheduler,
+            .v9a,
+        }),
+    };
     pub const cyclone = CpuModel{
         .name = "cyclone",
         .llvm_name = "cyclone",
         .features = featureSet(&[_]Feature{
-            .apple_a7,
+            .alternate_sextload_cvt_f32_pattern,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .disable_latency_sched_heuristic,
+            .fuse_aes,
+            .fuse_crypto_eor,
+            .perfmon,
+            .v8a,
+            .zcm,
+            .zcz,
+            .zcz_fp_workaround,
         }),
     };
     pub const emag = CpuModel{
@@ -1763,33 +1924,68 @@ pub const cpu = struct {
         .name = "exynos_m3",
         .llvm_name = "exynos-m3",
         .features = featureSet(&[_]Feature{
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
             .crc,
             .crypto,
             .exynos_cheap_as_move,
             .force_32bit_jump_tables,
             .fuse_address,
             .fuse_aes,
+            .fuse_arith_logic,
             .fuse_csel,
             .fuse_literals,
             .lsl_fast,
             .perfmon,
-            .predictable_select_expensive,
             .use_postra_scheduler,
             .v8a,
+            .zcz,
         }),
     };
     pub const exynos_m4 = CpuModel{
         .name = "exynos_m4",
         .llvm_name = "exynos-m4",
         .features = featureSet(&[_]Feature{
-            .exynos_m4,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .dotprod,
+            .exynos_cheap_as_move,
+            .force_32bit_jump_tables,
+            .fullfp16,
+            .fuse_address,
+            .fuse_aes,
+            .fuse_arith_logic,
+            .fuse_csel,
+            .fuse_literals,
+            .lsl_fast,
+            .perfmon,
+            .use_postra_scheduler,
+            .v8_2a,
+            .zcz,
         }),
     };
     pub const exynos_m5 = CpuModel{
         .name = "exynos_m5",
         .llvm_name = "exynos-m5",
         .features = featureSet(&[_]Feature{
-            .exynos_m4,
+            .arith_bcc_fusion,
+            .arith_cbz_fusion,
+            .crypto,
+            .dotprod,
+            .exynos_cheap_as_move,
+            .force_32bit_jump_tables,
+            .fullfp16,
+            .fuse_address,
+            .fuse_aes,
+            .fuse_arith_logic,
+            .fuse_csel,
+            .fuse_literals,
+            .lsl_fast,
+            .perfmon,
+            .use_postra_scheduler,
+            .v8_2a,
+            .zcz,
         }),
     };
     pub const falkor = CpuModel{
@@ -1835,32 +2031,86 @@ pub const cpu = struct {
             .zcz,
         }),
     };
+    pub const neoverse_512tvb = CpuModel{
+        .name = "neoverse_512tvb",
+        .llvm_name = "neoverse-512tvb",
+        .features = featureSet(&[_]Feature{
+            .bf16,
+            .ccdp,
+            .crypto,
+            .fp16fml,
+            .fuse_aes,
+            .i8mm,
+            .perfmon,
+            .rand,
+            .spe,
+            .ssbs,
+            .sve,
+            .use_postra_scheduler,
+            .v8_4a,
+        }),
+    };
     pub const neoverse_e1 = CpuModel{
         .name = "neoverse_e1",
         .llvm_name = "neoverse-e1",
         .features = featureSet(&[_]Feature{
-            .neoverse_e1,
+            .crypto,
+            .dotprod,
+            .fullfp16,
+            .fuse_aes,
+            .rcpc,
+            .ssbs,
+            .use_postra_scheduler,
+            .v8_2a,
         }),
     };
     pub const neoverse_n1 = CpuModel{
         .name = "neoverse_n1",
         .llvm_name = "neoverse-n1",
         .features = featureSet(&[_]Feature{
-            .neoverse_n1,
+            .crypto,
+            .dotprod,
+            .fullfp16,
+            .fuse_aes,
+            .rcpc,
+            .spe,
+            .ssbs,
+            .use_postra_scheduler,
+            .v8_2a,
         }),
     };
     pub const neoverse_n2 = CpuModel{
         .name = "neoverse_n2",
         .llvm_name = "neoverse-n2",
         .features = featureSet(&[_]Feature{
-            .neoverse_n2,
+            .bf16,
+            .crypto,
+            .ete,
+            .fuse_aes,
+            .i8mm,
+            .mte,
+            .sve2_bitperm,
+            .use_postra_scheduler,
+            .v8_5a,
         }),
     };
     pub const neoverse_v1 = CpuModel{
         .name = "neoverse_v1",
         .llvm_name = "neoverse-v1",
         .features = featureSet(&[_]Feature{
-            .neoverse_v1,
+            .bf16,
+            .ccdp,
+            .crypto,
+            .fp16fml,
+            .fuse_aes,
+            .i8mm,
+            .perfmon,
+            .rand,
+            .spe,
+            .ssbs,
+            .sve,
+            .use_postra_scheduler,
+            .v8_4a,
         }),
     };
     pub const saphira = CpuModel{
diff --git a/lib/std/target/amdgpu.zig b/lib/std/target/amdgpu.zig
index 2fb8a6fa80..7bf39a7830 100644
--- a/lib/std/target/amdgpu.zig
+++ b/lib/std/target/amdgpu.zig
@@ -65,7 +65,6 @@ pub const Feature = enum {
     ldsbankcount16,
     ldsbankcount32,
     load_store_opt,
-    localmemorysize0,
     localmemorysize32768,
     localmemorysize65536,
     mad_mac_f32_insts,
@@ -92,7 +91,6 @@ pub const Feature = enum {
     pk_fmac_f16_inst,
     promote_alloca,
     r128_a16,
-    register_banking,
     s_memrealtime,
     s_memtime_inst,
     scalar_atomics,
@@ -374,7 +372,6 @@ pub const all_features = blk: {
             .no_data_dep_hazard,
             .no_sdst_cmpx,
             .pk_fmac_f16_inst,
-            .register_banking,
             .s_memrealtime,
             .s_memtime_inst,
             .sdwa,
@@ -525,11 +522,6 @@ pub const all_features = blk: {
         .description = "Enable SI load/store optimizer pass",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.localmemorysize0)] = .{
-        .llvm_name = "localmemorysize0",
-        .description = "The size of local memory in bytes",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@enumToInt(Feature.localmemorysize32768)] = .{
         .llvm_name = "localmemorysize32768",
         .description = "The size of local memory in bytes",
@@ -660,11 +652,6 @@ pub const all_features = blk: {
         .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.register_banking)] = .{
-        .llvm_name = "register-banking",
-        .description = "Has register banking",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@enumToInt(Feature.s_memrealtime)] = .{
         .llvm_name = "s-memrealtime",
         .description = "Has s_memrealtime instruction",
diff --git a/lib/std/target/arm.zig b/lib/std/target/arm.zig
index 42e5f3bfdb..e3f04ebbd4 100644
--- a/lib/std/target/arm.zig
+++ b/lib/std/target/arm.zig
@@ -36,6 +36,7 @@ pub const Feature = enum {
     execute_only,
     expand_fp_mlx,
     exynos,
+    fix_cmse_cve_2021_35465,
     fp16,
     fp16fml,
     fp64,
@@ -71,8 +72,13 @@ pub const Feature = enum {
     has_v8_5a,
     has_v8_6a,
     has_v8_7a,
+    has_v8_8a,
     has_v8m,
     has_v8m_main,
+    has_v9_1a,
+    has_v9_2a,
+    has_v9_3a,
+    has_v9a,
     hwdiv,
     hwdiv_arm,
     i8mm,
@@ -95,10 +101,12 @@ pub const Feature = enum {
     neon_fpmovs,
     neonfp,
     no_branch_predictor,
+    no_bti_at_return_twice,
     no_movt,
     no_neg_immediates,
     noarm,
     nonpipelined_vfp,
+    pacbti,
     perfmon,
     prefer_ishst,
     prefer_vmovsr,
@@ -157,10 +165,15 @@ pub const Feature = enum {
     v8_5a,
     v8_6a,
     v8_7a,
+    v8_8a,
     v8a,
     v8m,
     v8m_main,
     v8r,
+    v9_1a,
+    v9_2a,
+    v9_3a,
+    v9a,
     vfp2,
     vfp2sp,
     vfp3,
@@ -390,6 +403,11 @@ pub const all_features = blk: {
             .zcz,
         }),
     };
+    result[@enumToInt(Feature.fix_cmse_cve_2021_35465)] = .{
+        .llvm_name = "fix-cmse-cve-2021-35465",
+        .description = "Mitigate against the cve-2021-35465 security vulnurability",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.fp16)] = .{
         .llvm_name = "fp16",
         .description = "Enable half-precision floating point",
@@ -553,7 +571,6 @@ pub const all_features = blk: {
         .dependencies = featureSet(&[_]Feature{
             .has_v6t2,
             .has_v7clrex,
-            .perfmon,
         }),
     };
     result[@enumToInt(Feature.has_v7clrex)] = .{
@@ -567,6 +584,7 @@ pub const all_features = blk: {
         .dependencies = featureSet(&[_]Feature{
             .acquire_release,
             .has_v7,
+            .perfmon,
         }),
     };
     result[@enumToInt(Feature.has_v8_1a)] = .{
@@ -629,6 +647,13 @@ pub const all_features = blk: {
             .has_v8_6a,
         }),
     };
+    result[@enumToInt(Feature.has_v8_8a)] = .{
+        .llvm_name = "v8.8a",
+        .description = "Support ARM v8.8a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .has_v8_7a,
+        }),
+    };
     result[@enumToInt(Feature.has_v8m)] = .{
         .llvm_name = "v8m",
         .description = "Support ARM v8M Baseline instructions",
@@ -643,6 +668,37 @@ pub const all_features = blk: {
             .has_v7,
         }),
     };
+    result[@enumToInt(Feature.has_v9_1a)] = .{
+        .llvm_name = "v9.1a",
+        .description = "Support ARM v9.1a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .has_v8_6a,
+            .has_v9a,
+        }),
+    };
+    result[@enumToInt(Feature.has_v9_2a)] = .{
+        .llvm_name = "v9.2a",
+        .description = "Support ARM v9.2a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .has_v8_7a,
+            .has_v9_1a,
+        }),
+    };
+    result[@enumToInt(Feature.has_v9_3a)] = .{
+        .llvm_name = "v9.3a",
+        .description = "Support ARM v9.3a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .has_v8_8a,
+            .has_v9_2a,
+        }),
+    };
+    result[@enumToInt(Feature.has_v9a)] = .{
+        .llvm_name = "v9a",
+        .description = "Support ARM v9a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .has_v8_5a,
+        }),
+    };
     result[@enumToInt(Feature.hwdiv)] = .{
         .llvm_name = "hwdiv",
         .description = "Enable divide instructions in Thumb",
@@ -769,6 +825,11 @@ pub const all_features = blk: {
         .description = "Has no branch predictor",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.no_bti_at_return_twice)] = .{
+        .llvm_name = "no-bti-at-return-twice",
+        .description = "Don't place a BTI instruction after a return-twice",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.no_movt)] = .{
         .llvm_name = "no-movt",
         .description = "Don't use movt/movw pairs for 32-bit imms",
@@ -789,6 +850,11 @@ pub const all_features = blk: {
         .description = "VFP instructions are not pipelined",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.pacbti)] = .{
+        .llvm_name = "pacbti",
+        .description = "Enable Pointer Authentication and Branch Target Identification",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.perfmon)] = .{
         .llvm_name = "perfmon",
         .description = "Enable support for Performance Monitor extensions",
@@ -1066,6 +1132,7 @@ pub const all_features = blk: {
             .dsp,
             .has_v7,
             .neon,
+            .perfmon,
         }),
     };
     result[@enumToInt(Feature.v7em)] = .{
@@ -1108,6 +1175,7 @@ pub const all_features = blk: {
             .dsp,
             .has_v7,
             .hwdiv,
+            .perfmon,
             .rclass,
         }),
     };
@@ -1128,6 +1196,7 @@ pub const all_features = blk: {
             .has_v7,
             .mp,
             .neon,
+            .perfmon,
             .trustzone,
             .virtualization,
         }),
@@ -1266,6 +1335,23 @@ pub const all_features = blk: {
             .virtualization,
         }),
     };
+    result[@enumToInt(Feature.v8_8a)] = .{
+        .llvm_name = "armv8.8-a",
+        .description = "ARMv88a architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .aclass,
+            .crc,
+            .crypto,
+            .db,
+            .dsp,
+            .fp_armv8,
+            .has_v8_8a,
+            .mp,
+            .ras,
+            .trustzone,
+            .virtualization,
+        }),
+    };
     result[@enumToInt(Feature.v8a)] = .{
         .llvm_name = "armv8-a",
         .description = "ARMv8a architecture",
@@ -1328,6 +1414,71 @@ pub const all_features = blk: {
             .virtualization,
         }),
     };
+    result[@enumToInt(Feature.v9_1a)] = .{
+        .llvm_name = "armv9.1-a",
+        .description = "ARMv91a architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .aclass,
+            .crc,
+            .db,
+            .dsp,
+            .fp_armv8,
+            .has_v9_1a,
+            .mp,
+            .ras,
+            .trustzone,
+            .virtualization,
+        }),
+    };
+    result[@enumToInt(Feature.v9_2a)] = .{
+        .llvm_name = "armv9.2-a",
+        .description = "ARMv92a architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .aclass,
+            .crc,
+            .db,
+            .dsp,
+            .fp_armv8,
+            .has_v9_2a,
+            .mp,
+            .ras,
+            .trustzone,
+            .virtualization,
+        }),
+    };
+    result[@enumToInt(Feature.v9_3a)] = .{
+        .llvm_name = "armv9.3-a",
+        .description = "ARMv93a architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .aclass,
+            .crc,
+            .crypto,
+            .db,
+            .dsp,
+            .fp_armv8,
+            .has_v9_3a,
+            .mp,
+            .ras,
+            .trustzone,
+            .virtualization,
+        }),
+    };
+    result[@enumToInt(Feature.v9a)] = .{
+        .llvm_name = "armv9-a",
+        .description = "ARMv9a architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .aclass,
+            .crc,
+            .db,
+            .dsp,
+            .fp_armv8,
+            .has_v9a,
+            .mp,
+            .ras,
+            .trustzone,
+            .virtualization,
+        }),
+    };
     result[@enumToInt(Feature.vfp2)] = .{
         .llvm_name = "vfp2",
         .description = "Enable VFP2 instructions",
@@ -1781,6 +1932,16 @@ pub const cpu = struct {
             .vmlx_hazards,
         }),
     };
+    pub const cortex_a710 = CpuModel{
+        .name = "cortex_a710",
+        .llvm_name = "cortex-a710",
+        .features = featureSet(&[_]Feature{
+            .bf16,
+            .fp16fml,
+            .i8mm,
+            .v9a,
+        }),
+    };
     pub const cortex_a72 = CpuModel{
         .name = "cortex_a72",
         .llvm_name = "cortex-a72",
@@ -1933,6 +2094,7 @@ pub const cpu = struct {
         .llvm_name = "cortex-m33",
         .features = featureSet(&[_]Feature{
             .dsp,
+            .fix_cmse_cve_2021_35465,
             .fp_armv8d16sp,
             .loop_align,
             .no_branch_predictor,
@@ -1947,6 +2109,7 @@ pub const cpu = struct {
         .llvm_name = "cortex-m35p",
         .features = featureSet(&[_]Feature{
             .dsp,
+            .fix_cmse_cve_2021_35465,
             .fp_armv8d16sp,
             .loop_align,
             .no_branch_predictor,
@@ -1973,6 +2136,7 @@ pub const cpu = struct {
         .name = "cortex_m55",
         .llvm_name = "cortex-m55",
         .features = featureSet(&[_]Feature{
+            .fix_cmse_cve_2021_35465,
             .fp_armv8d16,
             .loop_align,
             .mve_fp,
@@ -2079,6 +2243,15 @@ pub const cpu = struct {
             .v8_2a,
         }),
     };
+    pub const cortex_x1c = CpuModel{
+        .name = "cortex_x1c",
+        .llvm_name = "cortex-x1c",
+        .features = featureSet(&[_]Feature{
+            .dotprod,
+            .fullfp16,
+            .v8_2a,
+        }),
+    };
     pub const cyclone = CpuModel{
         .name = "cyclone",
         .llvm_name = "cyclone",
diff --git a/lib/std/target/avr.zig b/lib/std/target/avr.zig
index f30a8a788c..cfeec05f8e 100644
--- a/lib/std/target/avr.zig
+++ b/lib/std/target/avr.zig
@@ -583,6 +583,20 @@ pub const cpu = struct {
             .avr35,
         }),
     };
+    pub const ata5702m322 = CpuModel{
+        .name = "ata5702m322",
+        .llvm_name = "ata5702m322",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
+    pub const ata5782 = CpuModel{
+        .name = "ata5782",
+        .llvm_name = "ata5782",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
     pub const ata5790 = CpuModel{
         .name = "ata5790",
         .llvm_name = "ata5790",
@@ -590,6 +604,20 @@ pub const cpu = struct {
             .avr5,
         }),
     };
+    pub const ata5790n = CpuModel{
+        .name = "ata5790n",
+        .llvm_name = "ata5790n",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
+    pub const ata5791 = CpuModel{
+        .name = "ata5791",
+        .llvm_name = "ata5791",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
     pub const ata5795 = CpuModel{
         .name = "ata5795",
         .llvm_name = "ata5795",
@@ -597,6 +625,13 @@ pub const cpu = struct {
             .avr5,
         }),
     };
+    pub const ata5831 = CpuModel{
+        .name = "ata5831",
+        .llvm_name = "ata5831",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
     pub const ata6285 = CpuModel{
         .name = "ata6285",
         .llvm_name = "ata6285",
@@ -618,6 +653,55 @@ pub const cpu = struct {
             .avr4,
         }),
     };
+    pub const ata6612c = CpuModel{
+        .name = "ata6612c",
+        .llvm_name = "ata6612c",
+        .features = featureSet(&[_]Feature{
+            .avr4,
+        }),
+    };
+    pub const ata6613c = CpuModel{
+        .name = "ata6613c",
+        .llvm_name = "ata6613c",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
+    pub const ata6614q = CpuModel{
+        .name = "ata6614q",
+        .llvm_name = "ata6614q",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
+    pub const ata6617c = CpuModel{
+        .name = "ata6617c",
+        .llvm_name = "ata6617c",
+        .features = featureSet(&[_]Feature{
+            .avr35,
+        }),
+    };
+    pub const ata664251 = CpuModel{
+        .name = "ata664251",
+        .llvm_name = "ata664251",
+        .features = featureSet(&[_]Feature{
+            .avr35,
+        }),
+    };
+    pub const ata8210 = CpuModel{
+        .name = "ata8210",
+        .llvm_name = "ata8210",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
+    pub const ata8510 = CpuModel{
+        .name = "ata8510",
+        .llvm_name = "ata8510",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
     pub const atmega103 = CpuModel{
         .name = "atmega103",
         .llvm_name = "atmega103",
@@ -1347,6 +1431,13 @@ pub const cpu = struct {
             .avr5,
         }),
     };
+    pub const atmega64hve2 = CpuModel{
+        .name = "atmega64hve2",
+        .llvm_name = "atmega64hve2",
+        .features = featureSet(&[_]Feature{
+            .avr5,
+        }),
+    };
     pub const atmega64m1 = CpuModel{
         .name = "atmega64m1",
         .llvm_name = "atmega64m1",
@@ -1510,6 +1601,48 @@ pub const cpu = struct {
             .avr1,
         }),
     };
+    pub const attiny1604 = CpuModel{
+        .name = "attiny1604",
+        .llvm_name = "attiny1604",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny1606 = CpuModel{
+        .name = "attiny1606",
+        .llvm_name = "attiny1606",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny1607 = CpuModel{
+        .name = "attiny1607",
+        .llvm_name = "attiny1607",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny1614 = CpuModel{
+        .name = "attiny1614",
+        .llvm_name = "attiny1614",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny1616 = CpuModel{
+        .name = "attiny1616",
+        .llvm_name = "attiny1616",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny1617 = CpuModel{
+        .name = "attiny1617",
+        .llvm_name = "attiny1617",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
     pub const attiny1634 = CpuModel{
         .name = "attiny1634",
         .llvm_name = "attiny1634",
@@ -1531,6 +1664,34 @@ pub const cpu = struct {
             .avrtiny,
         }),
     };
+    pub const attiny202 = CpuModel{
+        .name = "attiny202",
+        .llvm_name = "attiny202",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny204 = CpuModel{
+        .name = "attiny204",
+        .llvm_name = "attiny204",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny212 = CpuModel{
+        .name = "attiny212",
+        .llvm_name = "attiny212",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny214 = CpuModel{
+        .name = "attiny214",
+        .llvm_name = "attiny214",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
     pub const attiny22 = CpuModel{
         .name = "attiny22",
         .llvm_name = "attiny22",
@@ -1602,6 +1763,20 @@ pub const cpu = struct {
             .avr1,
         }),
     };
+    pub const attiny3216 = CpuModel{
+        .name = "attiny3216",
+        .llvm_name = "attiny3216",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny3217 = CpuModel{
+        .name = "attiny3217",
+        .llvm_name = "attiny3217",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
     pub const attiny4 = CpuModel{
         .name = "attiny4",
         .llvm_name = "attiny4",
@@ -1616,6 +1791,55 @@ pub const cpu = struct {
             .avrtiny,
         }),
     };
+    pub const attiny402 = CpuModel{
+        .name = "attiny402",
+        .llvm_name = "attiny402",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny404 = CpuModel{
+        .name = "attiny404",
+        .llvm_name = "attiny404",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny406 = CpuModel{
+        .name = "attiny406",
+        .llvm_name = "attiny406",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny412 = CpuModel{
+        .name = "attiny412",
+        .llvm_name = "attiny412",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny414 = CpuModel{
+        .name = "attiny414",
+        .llvm_name = "attiny414",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny416 = CpuModel{
+        .name = "attiny416",
+        .llvm_name = "attiny416",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny417 = CpuModel{
+        .name = "attiny417",
+        .llvm_name = "attiny417",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
     pub const attiny4313 = CpuModel{
         .name = "attiny4313",
         .llvm_name = "attiny4313",
@@ -1686,6 +1910,48 @@ pub const cpu = struct {
             .avrtiny,
         }),
     };
+    pub const attiny804 = CpuModel{
+        .name = "attiny804",
+        .llvm_name = "attiny804",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny806 = CpuModel{
+        .name = "attiny806",
+        .llvm_name = "attiny806",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny807 = CpuModel{
+        .name = "attiny807",
+        .llvm_name = "attiny807",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny814 = CpuModel{
+        .name = "attiny814",
+        .llvm_name = "attiny814",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny816 = CpuModel{
+        .name = "attiny816",
+        .llvm_name = "attiny816",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
+    pub const attiny817 = CpuModel{
+        .name = "attiny817",
+        .llvm_name = "attiny817",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
     pub const attiny828 = CpuModel{
         .name = "attiny828",
         .llvm_name = "attiny828",
@@ -1945,6 +2211,13 @@ pub const cpu = struct {
             .xmegau,
         }),
     };
+    pub const atxmega32c3 = CpuModel{
+        .name = "atxmega32c3",
+        .llvm_name = "atxmega32c3",
+        .features = featureSet(&[_]Feature{
+            .xmegau,
+        }),
+    };
     pub const atxmega32c4 = CpuModel{
         .name = "atxmega32c4",
         .llvm_name = "atxmega32c4",
@@ -1952,6 +2225,13 @@ pub const cpu = struct {
             .xmegau,
         }),
     };
+    pub const atxmega32d3 = CpuModel{
+        .name = "atxmega32d3",
+        .llvm_name = "atxmega32d3",
+        .features = featureSet(&[_]Feature{
+            .xmega,
+        }),
+    };
     pub const atxmega32d4 = CpuModel{
         .name = "atxmega32d4",
         .llvm_name = "atxmega32d4",
diff --git a/lib/std/target/csky.zig b/lib/std/target/csky.zig
new file mode 100644
index 0000000000..9699ea4ab1
--- /dev/null
+++ b/lib/std/target/csky.zig
@@ -0,0 +1,163 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    @"10e60",
+    @"2e3",
+    @"3e3r1",
+    @"3e3r3",
+    @"3e7",
+    @"7e10",
+    btst16,
+    doloop,
+    e1,
+    e2,
+    elrw,
+    fpuv2_df,
+    fpuv2_sf,
+    fpuv3_df,
+    fpuv3_sf,
+    hard_float,
+    hard_float_abi,
+    java,
+    mp1e2,
+};
+
+pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.feature_set_fns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.feature_set_fns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.feature_set_fns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).Enum.fields.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@enumToInt(Feature.@"10e60")] = .{
+        .llvm_name = "10e60",
+        .description = "Support CSKY 10e60 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .@"7e10",
+        }),
+    };
+    result[@enumToInt(Feature.@"2e3")] = .{
+        .llvm_name = "2e3",
+        .description = "Support CSKY 2e3 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .e2,
+        }),
+    };
+    result[@enumToInt(Feature.@"3e3r1")] = .{
+        .llvm_name = "3e3r1",
+        .description = "Support CSKY 3e3r1 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.@"3e3r3")] = .{
+        .llvm_name = "3e3r3",
+        .description = "Support CSKY 3e3r3 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .doloop,
+        }),
+    };
+    result[@enumToInt(Feature.@"3e7")] = .{
+        .llvm_name = "3e7",
+        .description = "Support CSKY 3e7 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .@"2e3",
+        }),
+    };
+    result[@enumToInt(Feature.@"7e10")] = .{
+        .llvm_name = "7e10",
+        .description = "Support CSKY 7e10 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .@"3e7",
+        }),
+    };
+    result[@enumToInt(Feature.btst16)] = .{
+        .llvm_name = "btst16",
+        .description = "Use the 16-bit btsti instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.doloop)] = .{
+        .llvm_name = "doloop",
+        .description = "Enable doloop instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.e1)] = .{
+        .llvm_name = "e1",
+        .description = "Support CSKY e1 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .elrw,
+        }),
+    };
+    result[@enumToInt(Feature.e2)] = .{
+        .llvm_name = "e2",
+        .description = "Support CSKY e2 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .e1,
+        }),
+    };
+    result[@enumToInt(Feature.elrw)] = .{
+        .llvm_name = "elrw",
+        .description = "Use the extend LRW instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.fpuv2_df)] = .{
+        .llvm_name = "fpuv2_df",
+        .description = "Enable FPUv2 double float instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.fpuv2_sf)] = .{
+        .llvm_name = "fpuv2_sf",
+        .description = "Enable FPUv2 single float instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.fpuv3_df)] = .{
+        .llvm_name = "fpuv3_df",
+        .description = "Enable FPUv3 double float instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.fpuv3_sf)] = .{
+        .llvm_name = "fpuv3_sf",
+        .description = "Enable FPUv3 single float instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.hard_float)] = .{
+        .llvm_name = "hard-float",
+        .description = "Use hard floating point features",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.hard_float_abi)] = .{
+        .llvm_name = "hard-float-abi",
+        .description = "Use hard floating point ABI to pass args",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.java)] = .{
+        .llvm_name = "java",
+        .description = "Enable java instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.mp1e2)] = .{
+        .llvm_name = "mp1e2",
+        .description = "Support CSKY mp1e2 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .@"3e7",
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (result) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.Enum.fields[i].name;
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const generic = CpuModel{
+        .name = "generic",
+        .llvm_name = "generic",
+        .features = featureSet(&[_]Feature{}),
+    };
+};
diff --git a/lib/std/target/hexagon.zig b/lib/std/target/hexagon.zig
index de0e34aa3d..1bab66fb05 100644
--- a/lib/std/target/hexagon.zig
+++ b/lib/std/target/hexagon.zig
@@ -6,17 +6,21 @@ const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
     audio,
+    cabac,
     compound,
     duplex,
     hvx,
+    hvx_ieee_fp,
     hvx_length128b,
     hvx_length64b,
+    hvx_qfloat,
     hvxv60,
     hvxv62,
     hvxv65,
     hvxv66,
     hvxv67,
     hvxv68,
+    hvxv69,
     long_calls,
     mem_noshuf,
     memops,
@@ -37,6 +41,7 @@ pub const Feature = enum {
     v66,
     v67,
     v68,
+    v69,
     zreg,
 };
 
@@ -54,6 +59,11 @@ pub const all_features = blk: {
         .description = "Hexagon Audio extension instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.cabac)] = .{
+        .llvm_name = "cabac",
+        .description = "Emit the CABAC instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.compound)] = .{
         .llvm_name = "compound",
         .description = "Use compound instructions",
@@ -69,6 +79,11 @@ pub const all_features = blk: {
         .description = "Hexagon HVX instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.hvx_ieee_fp)] = .{
+        .llvm_name = "hvx-ieee-fp",
+        .description = "Hexagon HVX IEEE floating point instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.hvx_length128b)] = .{
         .llvm_name = "hvx-length128b",
         .description = "Hexagon HVX 128B instructions",
@@ -83,6 +98,11 @@ pub const all_features = blk: {
             .hvx,
         }),
     };
+    result[@enumToInt(Feature.hvx_qfloat)] = .{
+        .llvm_name = "hvx-qfloat",
+        .description = "Hexagon HVX QFloating point instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.hvxv60)] = .{
         .llvm_name = "hvxv60",
         .description = "Hexagon HVX instructions",
@@ -126,6 +146,13 @@ pub const all_features = blk: {
             .hvxv67,
         }),
     };
+    result[@enumToInt(Feature.hvxv69)] = .{
+        .llvm_name = "hvxv69",
+        .description = "Hexagon HVX instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .hvxv68,
+        }),
+    };
     result[@enumToInt(Feature.long_calls)] = .{
         .llvm_name = "long-calls",
         .description = "Use constant-extended calls",
@@ -230,6 +257,11 @@ pub const all_features = blk: {
         .description = "Enable Hexagon V68 architecture",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.v69)] = .{
+        .llvm_name = "v69",
+        .description = "Enable Hexagon V69 architecture",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.zreg)] = .{
         .llvm_name = "zreg",
         .description = "Hexagon ZReg extension instructions",
@@ -248,6 +280,7 @@ pub const cpu = struct {
         .name = "generic",
         .llvm_name = "generic",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .memops,
@@ -264,6 +297,7 @@ pub const cpu = struct {
         .name = "hexagonv5",
         .llvm_name = "hexagonv5",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .memops,
@@ -278,6 +312,7 @@ pub const cpu = struct {
         .name = "hexagonv55",
         .llvm_name = "hexagonv55",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .memops,
@@ -293,6 +328,7 @@ pub const cpu = struct {
         .name = "hexagonv60",
         .llvm_name = "hexagonv60",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .memops,
@@ -309,6 +345,7 @@ pub const cpu = struct {
         .name = "hexagonv62",
         .llvm_name = "hexagonv62",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .memops,
@@ -326,6 +363,7 @@ pub const cpu = struct {
         .name = "hexagonv65",
         .llvm_name = "hexagonv65",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .mem_noshuf,
@@ -344,6 +382,7 @@ pub const cpu = struct {
         .name = "hexagonv66",
         .llvm_name = "hexagonv66",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .mem_noshuf,
@@ -363,6 +402,7 @@ pub const cpu = struct {
         .name = "hexagonv67",
         .llvm_name = "hexagonv67",
         .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .mem_noshuf,
@@ -403,6 +443,29 @@ pub const cpu = struct {
         .name = "hexagonv68",
         .llvm_name = "hexagonv68",
         .features = featureSet(&[_]Feature{
+            .cabac,
+            .compound,
+            .duplex,
+            .mem_noshuf,
+            .memops,
+            .nvj,
+            .nvs,
+            .small_data,
+            .v5,
+            .v55,
+            .v60,
+            .v62,
+            .v65,
+            .v66,
+            .v67,
+            .v68,
+        }),
+    };
+    pub const hexagonv69 = CpuModel{
+        .name = "hexagonv69",
+        .llvm_name = "hexagonv69",
+        .features = featureSet(&[_]Feature{
+            .cabac,
             .compound,
             .duplex,
             .mem_noshuf,
@@ -418,6 +481,7 @@ pub const cpu = struct {
             .v66,
             .v67,
             .v68,
+            .v69,
         }),
     };
 };
diff --git a/lib/std/target/nvptx.zig b/lib/std/target/nvptx.zig
index 0a5581090e..4863d82bde 100644
--- a/lib/std/target/nvptx.zig
+++ b/lib/std/target/nvptx.zig
@@ -19,6 +19,9 @@ pub const Feature = enum {
     ptx70,
     ptx71,
     ptx72,
+    ptx73,
+    ptx74,
+    ptx75,
     sm_20,
     sm_21,
     sm_30,
@@ -117,6 +120,21 @@ pub const all_features = blk: {
         .description = "Use PTX version 7.2",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.ptx73)] = .{
+        .llvm_name = "ptx73",
+        .description = "Use PTX version 7.3",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.ptx74)] = .{
+        .llvm_name = "ptx74",
+        .description = "Use PTX version 7.4",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.ptx75)] = .{
+        .llvm_name = "ptx75",
+        .description = "Use PTX version 7.5",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.sm_20)] = .{
         .llvm_name = "sm_20",
         .description = "Target SM 2.0",
diff --git a/lib/std/target/powerpc.zig b/lib/std/target/powerpc.zig
index 3145b2b14c..513a9ad8e0 100644
--- a/lib/std/target/powerpc.zig
+++ b/lib/std/target/powerpc.zig
@@ -29,14 +29,24 @@ pub const Feature = enum {
     frsqrte,
     frsqrtes,
     fsqrt,
+    fuse_add_logical,
     fuse_addi_load,
     fuse_addis_load,
+    fuse_arith_add,
+    fuse_back2back,
+    fuse_cmp,
+    fuse_logical,
+    fuse_logical_add,
+    fuse_sha3,
     fuse_store,
+    fuse_wideimm,
+    fuse_zeromove,
     fusion,
     hard_float,
     htm,
     icbt,
     invariant_function_descriptors,
+    isa_v206_instructions,
     isa_v207_instructions,
     isa_v30_instructions,
     isa_v31_instructions,
@@ -235,6 +245,13 @@ pub const all_features = blk: {
             .fpu,
         }),
     };
+    result[@enumToInt(Feature.fuse_add_logical)] = .{
+        .llvm_name = "fuse-add-logical",
+        .description = "Target supports Add with Logical Operations fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
     result[@enumToInt(Feature.fuse_addi_load)] = .{
         .llvm_name = "fuse-addi-load",
         .description = "Power8 Addi-Load fusion",
@@ -249,6 +266,48 @@ pub const all_features = blk: {
             .fusion,
         }),
     };
+    result[@enumToInt(Feature.fuse_arith_add)] = .{
+        .llvm_name = "fuse-arith-add",
+        .description = "Target supports Arithmetic Operations with Add fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
+    result[@enumToInt(Feature.fuse_back2back)] = .{
+        .llvm_name = "fuse-back2back",
+        .description = "Target supports general back to back fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
+    result[@enumToInt(Feature.fuse_cmp)] = .{
+        .llvm_name = "fuse-cmp",
+        .description = "Target supports Comparison Operations fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
+    result[@enumToInt(Feature.fuse_logical)] = .{
+        .llvm_name = "fuse-logical",
+        .description = "Target supports Logical Operations fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
+    result[@enumToInt(Feature.fuse_logical_add)] = .{
+        .llvm_name = "fuse-logical-add",
+        .description = "Target supports Logical with Add Operations fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
+    result[@enumToInt(Feature.fuse_sha3)] = .{
+        .llvm_name = "fuse-sha3",
+        .description = "Target supports SHA3 assist fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
     result[@enumToInt(Feature.fuse_store)] = .{
         .llvm_name = "fuse-store",
         .description = "Target supports store clustering",
@@ -256,6 +315,20 @@ pub const all_features = blk: {
             .fusion,
         }),
     };
+    result[@enumToInt(Feature.fuse_wideimm)] = .{
+        .llvm_name = "fuse-wideimm",
+        .description = "Target supports Wide-Immediate fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
+    result[@enumToInt(Feature.fuse_zeromove)] = .{
+        .llvm_name = "fuse-zeromove",
+        .description = "Target supports move to SPR with branch fusion",
+        .dependencies = featureSet(&[_]Feature{
+            .fusion,
+        }),
+    };
     result[@enumToInt(Feature.fusion)] = .{
         .llvm_name = "fusion",
         .description = "Target supports instruction fusion",
@@ -281,6 +354,11 @@ pub const all_features = blk: {
         .description = "Assume function descriptors are invariant",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.isa_v206_instructions)] = .{
+        .llvm_name = "isa-v206-instructions",
+        .description = "Enable instructions in ISA 2.06.",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.isa_v207_instructions)] = .{
         .llvm_name = "isa-v207-instructions",
         .description = "Enable instructions in ISA 2.07.",
@@ -707,9 +785,15 @@ pub const cpu = struct {
             .frsqrte,
             .frsqrtes,
             .fsqrt,
+            .fuse_add_logical,
+            .fuse_arith_add,
+            .fuse_logical,
+            .fuse_logical_add,
+            .fuse_sha3,
             .fuse_store,
             .htm,
             .icbt,
+            .isa_v206_instructions,
             .isel,
             .ldbrx,
             .lfiwax,
@@ -817,6 +901,7 @@ pub const cpu = struct {
             .fuse_addis_load,
             .htm,
             .icbt,
+            .isa_v206_instructions,
             .isa_v207_instructions,
             .isel,
             .ldbrx,
@@ -851,9 +936,15 @@ pub const cpu = struct {
             .frsqrte,
             .frsqrtes,
             .fsqrt,
+            .fuse_add_logical,
+            .fuse_arith_add,
+            .fuse_logical,
+            .fuse_logical_add,
+            .fuse_sha3,
             .fuse_store,
             .htm,
             .icbt,
+            .isa_v206_instructions,
             .isel,
             .ldbrx,
             .lfiwax,
@@ -985,6 +1076,7 @@ pub const cpu = struct {
             .frsqrte,
             .frsqrtes,
             .fsqrt,
+            .isa_v206_instructions,
             .isel,
             .ldbrx,
             .lfiwax,
@@ -1019,6 +1111,7 @@ pub const cpu = struct {
             .fuse_addis_load,
             .htm,
             .icbt,
+            .isa_v206_instructions,
             .isa_v207_instructions,
             .isel,
             .ldbrx,
@@ -1055,6 +1148,7 @@ pub const cpu = struct {
             .fsqrt,
             .htm,
             .icbt,
+            .isa_v206_instructions,
             .isel,
             .ldbrx,
             .lfiwax,
diff --git a/lib/std/target/riscv.zig b/lib/std/target/riscv.zig
index 70a8f73245..7d2ee7e140 100644
--- a/lib/std/target/riscv.zig
+++ b/lib/std/target/riscv.zig
@@ -10,22 +10,12 @@ pub const Feature = enum {
     c,
     d,
     e,
-    experimental_b,
-    experimental_v,
-    experimental_zba,
-    experimental_zbb,
-    experimental_zbc,
     experimental_zbe,
     experimental_zbf,
     experimental_zbm,
     experimental_zbp,
-    experimental_zbproposedc,
     experimental_zbr,
-    experimental_zbs,
     experimental_zbt,
-    experimental_zfh,
-    experimental_zvamo,
-    experimental_zvlsseg,
     f,
     m,
     no_rvc_hints,
@@ -62,6 +52,46 @@ pub const Feature = enum {
     reserve_x8,
     reserve_x9,
     save_restore,
+    v,
+    zba,
+    zbb,
+    zbc,
+    zbkb,
+    zbkc,
+    zbkx,
+    zbs,
+    zdinx,
+    zfh,
+    zfhmin,
+    zfinx,
+    zhinx,
+    zhinxmin,
+    zk,
+    zkn,
+    zknd,
+    zkne,
+    zknh,
+    zkr,
+    zks,
+    zksed,
+    zksh,
+    zkt,
+    zve32f,
+    zve32x,
+    zve64d,
+    zve64f,
+    zve64x,
+    zvl1024b,
+    zvl128b,
+    zvl16384b,
+    zvl2048b,
+    zvl256b,
+    zvl32768b,
+    zvl32b,
+    zvl4096b,
+    zvl512b,
+    zvl64b,
+    zvl8192b,
 };
 
 pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
@@ -100,103 +130,36 @@ pub const all_features = blk: {
         .description = "Implements RV32E (provides 16 rather than 32 GPRs)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_b)] = .{
-        .llvm_name = "experimental-b",
-        .description = "'B' (Bit Manipulation Instructions)",
-        .dependencies = featureSet(&[_]Feature{
-            .experimental_zba,
-            .experimental_zbb,
-            .experimental_zbc,
-            .experimental_zbe,
-            .experimental_zbf,
-            .experimental_zbm,
-            .experimental_zbp,
-            .experimental_zbr,
-            .experimental_zbs,
-            .experimental_zbt,
-        }),
-    };
-    result[@enumToInt(Feature.experimental_v)] = .{
-        .llvm_name = "experimental-v",
-        .description = "'V' (Vector Instructions)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@enumToInt(Feature.experimental_zba)] = .{
-        .llvm_name = "experimental-zba",
-        .description = "'Zba' (Address calculation 'B' Instructions)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@enumToInt(Feature.experimental_zbb)] = .{
-        .llvm_name = "experimental-zbb",
-        .description = "'Zbb' (Base 'B' Instructions)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@enumToInt(Feature.experimental_zbc)] = .{
-        .llvm_name = "experimental-zbc",
-        .description = "'Zbc' (Carry-Less 'B' Instructions)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@enumToInt(Feature.experimental_zbe)] = .{
         .llvm_name = "experimental-zbe",
-        .description = "'Zbe' (Extract-Deposit 'B' Instructions)",
+        .description = "'Zbe' (Extract-Deposit 'Zb' Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.experimental_zbf)] = .{
         .llvm_name = "experimental-zbf",
-        .description = "'Zbf' (Bit-Field 'B' Instructions)",
+        .description = "'Zbf' (Bit-Field 'Zb' Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.experimental_zbm)] = .{
         .llvm_name = "experimental-zbm",
-        .description = "'Zbm' (Matrix 'B' Instructions)",
+        .description = "'Zbm' (Matrix 'Zb' Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.experimental_zbp)] = .{
         .llvm_name = "experimental-zbp",
-        .description = "'Zbp' (Permutation 'B' Instructions)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@enumToInt(Feature.experimental_zbproposedc)] = .{
-        .llvm_name = "experimental-zbproposedc",
-        .description = "'Zbproposedc' (Proposed Compressed 'B' Instructions)",
+        .description = "'Zbp' (Permutation 'Zb' Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.experimental_zbr)] = .{
         .llvm_name = "experimental-zbr",
-        .description = "'Zbr' (Polynomial Reduction 'B' Instructions)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@enumToInt(Feature.experimental_zbs)] = .{
-        .llvm_name = "experimental-zbs",
-        .description = "'Zbs' (Single-Bit 'B' Instructions)",
+        .description = "'Zbr' (Polynomial Reduction 'Zb' Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.experimental_zbt)] = .{
         .llvm_name = "experimental-zbt",
-        .description = "'Zbt' (Ternary 'B' Instructions)",
+        .description = "'Zbt' (Ternary 'Zb' Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_zfh)] = .{
-        .llvm_name = "experimental-zfh",
-        .description = "'Zfh' (Half-Precision Floating-Point)",
-        .dependencies = featureSet(&[_]Feature{
-            .f,
-        }),
-    };
-    result[@enumToInt(Feature.experimental_zvamo)] = .{
-        .llvm_name = "experimental-zvamo",
-        .description = "'Zvamo' (Vector AMO Operations)",
-        .dependencies = featureSet(&[_]Feature{
-            .experimental_v,
-        }),
-    };
-    result[@enumToInt(Feature.experimental_zvlsseg)] = .{
-        .llvm_name = "experimental-zvlsseg",
-        .description = "'Zvlsseg' (Vector segment load/store instructions)",
-        .dependencies = featureSet(&[_]Feature{
-            .experimental_v,
-        }),
-    };
     result[@enumToInt(Feature.f)] = .{
         .llvm_name = "f",
         .description = "'F' (Single-Precision Floating-Point)",
@@ -377,6 +340,268 @@ pub const all_features = blk: {
         .description = "Enable save/restore.",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.v)] = .{
+        .llvm_name = "v",
+        .description = "'V' (Vector Extension for Application Processors)",
+        .dependencies = featureSet(&[_]Feature{
+            .d,
+            .zvl128b,
+        }),
+    };
+    result[@enumToInt(Feature.zba)] = .{
+        .llvm_name = "zba",
+        .description = "'Zba' (Address Generation Instructions)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zbb)] = .{
+        .llvm_name = "zbb",
+        .description = "'Zbb' (Basic Bit-Manipulation)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zbc)] = .{
+        .llvm_name = "zbc",
+        .description = "'Zbc' (Carry-Less Multiplication)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zbkb)] = .{
+        .llvm_name = "zbkb",
+        .description = "'Zbkb' (Bitmanip instructions for Cryptography)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zbkc)] = .{
+        .llvm_name = "zbkc",
+        .description = "'Zbkc' (Carry-less multiply instructions for Cryptography)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zbkx)] = .{
+        .llvm_name = "zbkx",
+        .description = "'Zbkx' (Crossbar permutation instructions)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zbs)] = .{
+        .llvm_name = "zbs",
+        .description = "'Zbs' (Single-Bit Instructions)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zdinx)] = .{
+        .llvm_name = "zdinx",
+        .description = "'Zdinx' (Double in Integer)",
+        .dependencies = featureSet(&[_]Feature{
+            .zfinx,
+        }),
+    };
+    result[@enumToInt(Feature.zfh)] = .{
+        .llvm_name = "zfh",
+        .description = "'Zfh' (Half-Precision Floating-Point)",
+        .dependencies = featureSet(&[_]Feature{
+            .f,
+        }),
+    };
+    result[@enumToInt(Feature.zfhmin)] = .{
+        .llvm_name = "zfhmin",
+        .description = "'Zfhmin' (Half-Precision Floating-Point Minimal)",
+        .dependencies = featureSet(&[_]Feature{
+            .f,
+        }),
+    };
+    result[@enumToInt(Feature.zfinx)] = .{
+        .llvm_name = "zfinx",
+        .description = "'Zfinx' (Float in Integer)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zhinx)] = .{
+        .llvm_name = "zhinx",
+        .description = "'Zhinx' (Half Float in Integer)",
+        .dependencies = featureSet(&[_]Feature{
+            .zfinx,
+        }),
+    };
+    result[@enumToInt(Feature.zhinxmin)] = .{
+        .llvm_name = "zhinxmin",
+        .description = "'Zhinxmin' (Half Float in Integer Minimal)",
+        .dependencies = featureSet(&[_]Feature{
+            .zfinx,
+        }),
+    };
+    result[@enumToInt(Feature.zk)] = .{
+        .llvm_name = "zk",
+        .description = "'Zk' (Standard scalar cryptography extension)",
+        .dependencies = featureSet(&[_]Feature{
+            .zkn,
+            .zkr,
+            .zkt,
+        }),
+    };
+    result[@enumToInt(Feature.zkn)] = .{
+        .llvm_name = "zkn",
+        .description = "'Zkn' (NIST Algorithm Suite)",
+        .dependencies = featureSet(&[_]Feature{
+            .zbkb,
+            .zbkc,
+            .zbkx,
+            .zknd,
+            .zkne,
+            .zknh,
+        }),
+    };
+    result[@enumToInt(Feature.zknd)] = .{
+        .llvm_name = "zknd",
+        .description = "'Zknd' (NIST Suite: AES Decryption)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zkne)] = .{
+        .llvm_name = "zkne",
+        .description = "'Zkne' (NIST Suite: AES Encryption)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zknh)] = .{
+        .llvm_name = "zknh",
+        .description = "'Zknh' (NIST Suite: Hash Function Instructions)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zkr)] = .{
+        .llvm_name = "zkr",
+        .description = "'Zkr' (Entropy Source Extension)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zks)] = .{
+        .llvm_name = "zks",
+        .description = "'Zks' (ShangMi Algorithm Suite)",
+        .dependencies = featureSet(&[_]Feature{
+            .zbkb,
+            .zbkc,
+            .zbkx,
+            .zksed,
+            .zksh,
+        }),
+    };
+    result[@enumToInt(Feature.zksed)] = .{
+        .llvm_name = "zksed",
+        .description = "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zksh)] = .{
+        .llvm_name = "zksh",
+        .description = "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zkt)] = .{
+        .llvm_name = "zkt",
+        .description = "'Zkt' (Data Independent Execution Latency)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zve32f)] = .{
+        .llvm_name = "zve32f",
+        .description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
+        .dependencies = featureSet(&[_]Feature{
+            .zve32x,
+        }),
+    };
+    result[@enumToInt(Feature.zve32x)] = .{
+        .llvm_name = "zve32x",
+        .description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl32b,
+        }),
+    };
+    result[@enumToInt(Feature.zve64d)] = .{
+        .llvm_name = "zve64d",
+        .description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)",
+        .dependencies = featureSet(&[_]Feature{
+            .zve64f,
+        }),
+    };
+    result[@enumToInt(Feature.zve64f)] = .{
+        .llvm_name = "zve64f",
+        .description = "'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)",
+        .dependencies = featureSet(&[_]Feature{
+            .zve32f,
+            .zve64x,
+        }),
+    };
+    result[@enumToInt(Feature.zve64x)] = .{
+        .llvm_name = "zve64x",
+        .description = "'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)",
+        .dependencies = featureSet(&[_]Feature{
+            .zve32x,
+            .zvl64b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl1024b)] = .{
+        .llvm_name = "zvl1024b",
+        .description = "'Zvl' (Minimum Vector Length) 1024",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl512b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl128b)] = .{
+        .llvm_name = "zvl128b",
+        .description = "'Zvl' (Minimum Vector Length) 128",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl64b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl16384b)] = .{
+        .llvm_name = "zvl16384b",
+        .description = "'Zvl' (Minimum Vector Length) 16384",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl8192b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl2048b)] = .{
+        .llvm_name = "zvl2048b",
+        .description = "'Zvl' (Minimum Vector Length) 2048",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl1024b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl256b)] = .{
+        .llvm_name = "zvl256b",
+        .description = "'Zvl' (Minimum Vector Length) 256",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl128b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl32768b)] = .{
+        .llvm_name = "zvl32768b",
+        .description = "'Zvl' (Minimum Vector Length) 32768",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl16384b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl32b)] = .{
+        .llvm_name = "zvl32b",
+        .description = "'Zvl' (Minimum Vector Length) 32",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.zvl4096b)] = .{
+        .llvm_name = "zvl4096b",
+        .description = "'Zvl' (Minimum Vector Length) 4096",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl2048b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl512b)] = .{
+        .llvm_name = "zvl512b",
+        .description = "'Zvl' (Minimum Vector Length) 512",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl256b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl64b)] = .{
+        .llvm_name = "zvl64b",
+        .description = "'Zvl' (Minimum Vector Length) 64",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl32b,
+        }),
+    };
+    result[@enumToInt(Feature.zvl8192b)] = .{
+        .llvm_name = "zvl8192b",
+        .description = "'Zvl' (Minimum Vector Length) 8192",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl4096b,
+        }),
+    };
     const ti = @typeInfo(Feature);
     for (result) |*elem, i| {
         elem.index = i;
@@ -443,6 +668,33 @@ pub const cpu = struct {
             .@"64bit",
         }),
     };
+    pub const sifive_e20 = CpuModel{
+        .name = "sifive_e20",
+        .llvm_name = "sifive-e20",
+        .features = featureSet(&[_]Feature{
+            .c,
+            .m,
+        }),
+    };
+    pub const sifive_e21 = CpuModel{
+        .name = "sifive_e21",
+        .llvm_name = "sifive-e21",
+        .features = featureSet(&[_]Feature{
+            .a,
+            .c,
+            .m,
+        }),
+    };
+    pub const sifive_e24 = CpuModel{
+        .name = "sifive_e24",
+        .llvm_name = "sifive-e24",
+        .features = featureSet(&[_]Feature{
+            .a,
+            .c,
+            .f,
+            .m,
+        }),
+    };
     pub const sifive_e31 = CpuModel{
         .name = "sifive_e31",
         .llvm_name = "sifive-e31",
@@ -452,6 +704,16 @@ pub const cpu = struct {
             .m,
         }),
     };
+    pub const sifive_e34 = CpuModel{
+        .name = "sifive_e34",
+        .llvm_name = "sifive-e34",
+        .features = featureSet(&[_]Feature{
+            .a,
+            .c,
+            .f,
+            .m,
+        }),
+    };
     pub const sifive_e76 = CpuModel{
         .name = "sifive_e76",
         .llvm_name = "sifive-e76",
@@ -462,6 +724,48 @@ pub const cpu = struct {
             .m,
         }),
     };
+    pub const sifive_s21 = CpuModel{
+        .name = "sifive_s21",
+        .llvm_name = "sifive-s21",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .a,
+            .c,
+            .m,
+        }),
+    };
+    pub const sifive_s51 = CpuModel{
+        .name = "sifive_s51",
+        .llvm_name = "sifive-s51",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .a,
+            .c,
+            .m,
+        }),
+    };
+    pub const sifive_s54 = CpuModel{
+        .name = "sifive_s54",
+        .llvm_name = "sifive-s54",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .a,
+            .c,
+            .d,
+            .m,
+        }),
+    };
+    pub const sifive_s76 = CpuModel{
+        .name = "sifive_s76",
+        .llvm_name = "sifive-s76",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .a,
+            .c,
+            .d,
+            .m,
+        }),
+    };
     pub const sifive_u54 = CpuModel{
         .name = "sifive_u54",
         .llvm_name = "sifive-u54",
diff --git a/lib/std/target/wasm.zig b/lib/std/target/wasm.zig
index f120dfd7a5..deb0a05b12 100644
--- a/lib/std/target/wasm.zig
+++ b/lib/std/target/wasm.zig
@@ -12,6 +12,7 @@ pub const Feature = enum {
     mutable_globals,
     nontrapping_fptoint,
     reference_types,
+    relaxed_simd,
     sign_ext,
     simd128,
     tail_call,
@@ -61,6 +62,11 @@ pub const all_features = blk: {
         .description = "Enable reference types",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.relaxed_simd)] = .{
+        .llvm_name = "relaxed-simd",
+        .description = "Enable relaxed-simd instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.sign_ext)] = .{
         .llvm_name = "sign-ext",
         .description = "Enable sign extension operators",
diff --git a/lib/std/target/x86.zig b/lib/std/target/x86.zig
index c0a64c1077..8b80ba64bd 100644
--- a/lib/std/target/x86.zig
+++ b/lib/std/target/x86.zig
@@ -24,6 +24,7 @@ pub const Feature = enum {
     avx512dq,
     avx512er,
     avx512f,
+    avx512fp16,
     avx512ifma,
     avx512pf,
     avx512vbmi,
@@ -41,6 +42,7 @@ pub const Feature = enum {
     clwb,
     clzero,
     cmov,
+    crc32,
     cx16,
     cx8,
     enqcmd,
@@ -130,11 +132,13 @@ pub const Feature = enum {
     sse4a,
     sse_unaligned_mem,
     ssse3,
+    tagged_globals,
     tbm,
     tsxldtrk,
     uintr,
     use_aa,
     use_glm_div_sqrt_costs,
+    use_slm_arith_costs,
     vaes,
     vpclmulqdq,
     vzeroupper,
@@ -283,6 +287,15 @@ pub const all_features = blk: {
             .fma,
         }),
     };
+    result[@enumToInt(Feature.avx512fp16)] = .{
+        .llvm_name = "avx512fp16",
+        .description = "Support 16-bit floating point",
+        .dependencies = featureSet(&[_]Feature{
+            .avx512bw,
+            .avx512dq,
+            .avx512vl,
+        }),
+    };
     result[@enumToInt(Feature.avx512ifma)] = .{
         .llvm_name = "avx512ifma",
         .description = "Enable AVX-512 Integer Fused Multiple-Add",
@@ -386,6 +399,11 @@ pub const all_features = blk: {
         .description = "Enable conditional move instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.crc32)] = .{
+        .llvm_name = "crc32",
+        .description = "Enable SSE 4.2 CRC32 instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.cx16)] = .{
         .llvm_name = "cx16",
         .description = "64-bit with cmpxchg16b",
@@ -867,6 +885,11 @@ pub const all_features = blk: {
             .sse3,
         }),
     };
+    result[@enumToInt(Feature.tagged_globals)] = .{
+        .llvm_name = "tagged-globals",
+        .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.tbm)] = .{
         .llvm_name = "tbm",
         .description = "Enable TBM instructions",
@@ -892,6 +915,11 @@ pub const all_features = blk: {
         .description = "Use Goldmont specific floating point div/sqrt costs",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.use_slm_arith_costs)] = .{
+        .llvm_name = "use-slm-arith-costs",
+        .description = "Use Silvermont specific arithmetic costs",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.vaes)] = .{
         .llvm_name = "vaes",
         .description = "Promote selected AES instructions to AVX512/AVX registers",
@@ -977,45 +1005,6 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const _i386 = CpuModel{
-        .name = "_i386",
-        .llvm_name = "i386",
-        .features = featureSet(&[_]Feature{
-            .slow_unaligned_mem_16,
-            .vzeroupper,
-            .x87,
-        }),
-    };
-    pub const _i486 = CpuModel{
-        .name = "_i486",
-        .llvm_name = "i486",
-        .features = featureSet(&[_]Feature{
-            .slow_unaligned_mem_16,
-            .vzeroupper,
-            .x87,
-        }),
-    };
-    pub const _i586 = CpuModel{
-        .name = "_i586",
-        .llvm_name = "i586",
-        .features = featureSet(&[_]Feature{
-            .cx8,
-            .slow_unaligned_mem_16,
-            .vzeroupper,
-            .x87,
-        }),
-    };
-    pub const _i686 = CpuModel{
-        .name = "_i686",
-        .llvm_name = "i686",
-        .features = featureSet(&[_]Feature{
-            .cmov,
-            .cx8,
-            .slow_unaligned_mem_16,
-            .vzeroupper,
-            .x87,
-        }),
-    };
     pub const alderlake = CpuModel{
         .name = "alderlake",
         .llvm_name = "alderlake",
@@ -1029,6 +1018,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .false_deps_popcnt,
@@ -1281,6 +1271,7 @@ pub const cpu = struct {
             .aes,
             .branchfusion,
             .cmov,
+            .crc32,
             .cx16,
             .fast_11bytenop,
             .fast_scalar_shift_masks,
@@ -1309,6 +1300,7 @@ pub const cpu = struct {
             .bmi,
             .branchfusion,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .fast_11bytenop,
@@ -1342,6 +1334,7 @@ pub const cpu = struct {
             .bmi,
             .branchfusion,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .fast_11bytenop,
@@ -1378,6 +1371,7 @@ pub const cpu = struct {
             .bmi2,
             .branchfusion,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .fast_11bytenop,
@@ -1440,6 +1434,7 @@ pub const cpu = struct {
             .bmi,
             .bmi2,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .f16c,
@@ -1504,6 +1499,7 @@ pub const cpu = struct {
             .aes,
             .bmi,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .fast_15bytenop,
@@ -1568,6 +1564,7 @@ pub const cpu = struct {
             .bmi2,
             .clflushopt,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .fast_15bytenop,
@@ -1620,6 +1617,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .false_deps_popcnt,
@@ -1672,6 +1670,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .false_deps_popcnt,
@@ -1734,6 +1733,7 @@ pub const cpu = struct {
             .bmi,
             .bmi2,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .f16c,
@@ -1770,6 +1770,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .false_deps_popcnt,
@@ -1799,6 +1800,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .fxsr,
             .macrofusion,
@@ -1818,6 +1820,7 @@ pub const cpu = struct {
             .@"64bit",
             .avx,
             .cmov,
+            .crc32,
             .cx16,
             .false_deps_popcnt,
             .fast_15bytenop,
@@ -1871,6 +1874,7 @@ pub const cpu = struct {
             .aes,
             .clflushopt,
             .cmov,
+            .crc32,
             .cx16,
             .false_deps_popcnt,
             .fast_movbe,
@@ -1906,6 +1910,7 @@ pub const cpu = struct {
             .aes,
             .clflushopt,
             .cmov,
+            .crc32,
             .cx16,
             .fast_movbe,
             .fsgsbase,
@@ -1943,6 +1948,7 @@ pub const cpu = struct {
             .bmi,
             .bmi2,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .f16c,
@@ -1973,6 +1979,45 @@ pub const cpu = struct {
             .xsaveopt,
         }),
     };
+    pub const @"i386" = CpuModel{
+        .name = "i386",
+        .llvm_name = "i386",
+        .features = featureSet(&[_]Feature{
+            .slow_unaligned_mem_16,
+            .vzeroupper,
+            .x87,
+        }),
+    };
+    pub const @"i486" = CpuModel{
+        .name = "i486",
+        .llvm_name = "i486",
+        .features = featureSet(&[_]Feature{
+            .slow_unaligned_mem_16,
+            .vzeroupper,
+            .x87,
+        }),
+    };
+    pub const @"i586" = CpuModel{
+        .name = "i586",
+        .llvm_name = "i586",
+        .features = featureSet(&[_]Feature{
+            .cx8,
+            .slow_unaligned_mem_16,
+            .vzeroupper,
+            .x87,
+        }),
+    };
+    pub const @"i686" = CpuModel{
+        .name = "i686",
+        .llvm_name = "i686",
+        .features = featureSet(&[_]Feature{
+            .cmov,
+            .cx8,
+            .slow_unaligned_mem_16,
+            .vzeroupper,
+            .x87,
+        }),
+    };
     pub const icelake_client = CpuModel{
         .name = "icelake_client",
         .llvm_name = "icelake-client",
@@ -1992,6 +2037,7 @@ pub const cpu = struct {
             .bmi2,
             .clflushopt,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .fast_15bytenop,
@@ -2051,6 +2097,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .fast_15bytenop,
@@ -2098,6 +2145,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .false_deps_popcnt,
@@ -2203,6 +2251,7 @@ pub const cpu = struct {
             .bmi,
             .bmi2,
             .cmov,
+            .crc32,
             .cx16,
             .fast_gather,
             .fast_movbe,
@@ -2243,6 +2292,7 @@ pub const cpu = struct {
             .bmi,
             .bmi2,
             .cmov,
+            .crc32,
             .cx16,
             .fast_gather,
             .fast_movbe,
@@ -2285,6 +2335,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .fxsr,
             .macrofusion,
@@ -2523,6 +2574,7 @@ pub const cpu = struct {
             .bmi2,
             .clflushopt,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .fast_15bytenop,
@@ -2569,6 +2621,7 @@ pub const cpu = struct {
             .@"64bit",
             .avx,
             .cmov,
+            .crc32,
             .cx16,
             .false_deps_popcnt,
             .fast_15bytenop,
@@ -2600,11 +2653,10 @@ pub const cpu = struct {
             .avx512bf16,
             .avx512bitalg,
             .avx512cd,
-            .avx512dq,
+            .avx512fp16,
             .avx512ifma,
             .avx512vbmi,
             .avx512vbmi2,
-            .avx512vl,
             .avx512vnni,
             .avx512vp2intersect,
             .avx512vpopcntdq,
@@ -2615,6 +2667,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .enqcmd,
             .ermsb,
@@ -2671,6 +2724,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .false_deps_popcnt,
             .fast_7bytenop,
@@ -2690,6 +2744,7 @@ pub const cpu = struct {
             .slow_pmulld,
             .slow_two_mem_ops,
             .sse4_2,
+            .use_slm_arith_costs,
             .vzeroupper,
             .x87,
         }),
@@ -2710,6 +2765,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .false_deps_popcnt,
@@ -2757,6 +2813,7 @@ pub const cpu = struct {
             .bmi2,
             .clflushopt,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .f16c,
@@ -2808,6 +2865,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .false_deps_popcnt,
@@ -2849,6 +2907,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .false_deps_popcnt,
             .fast_7bytenop,
@@ -2868,6 +2927,7 @@ pub const cpu = struct {
             .slow_pmulld,
             .slow_two_mem_ops,
             .sse4_2,
+            .use_slm_arith_costs,
             .vzeroupper,
             .x87,
         }),
@@ -2893,6 +2953,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .ermsb,
             .fast_15bytenop,
@@ -2944,6 +3005,7 @@ pub const cpu = struct {
             .clflushopt,
             .clwb,
             .cmov,
+            .crc32,
             .cx16,
             .fast_movbe,
             .fsgsbase,
@@ -2979,6 +3041,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .fxsr,
             .macrofusion,
@@ -3037,6 +3100,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .cmov,
+            .crc32,
             .cx16,
             .false_deps_popcnt,
             .fast_15bytenop,
@@ -3065,6 +3129,7 @@ pub const cpu = struct {
             .bmi,
             .bmi2,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .false_deps_lzcnt_tzcnt,
@@ -3102,6 +3167,7 @@ pub const cpu = struct {
             .bmi,
             .bmi2,
             .cmov,
+            .crc32,
             .cx16,
             .false_deps_popcnt,
             .fast_15bytenop,
@@ -3156,13 +3222,16 @@ pub const cpu = struct {
             .clflushopt,
             .clzero,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .fast_15bytenop,
             .fast_bextr,
             .fast_lzcnt,
             .fast_movbe,
+            .fast_scalar_fsqrt,
             .fast_scalar_shift_masks,
+            .fast_vector_fsqrt,
             .fma,
             .fsgsbase,
             .fxsr,
@@ -3202,13 +3271,16 @@ pub const cpu = struct {
             .clwb,
             .clzero,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .fast_15bytenop,
             .fast_bextr,
             .fast_lzcnt,
             .fast_movbe,
+            .fast_scalar_fsqrt,
             .fast_scalar_shift_masks,
+            .fast_vector_fsqrt,
             .fma,
             .fsgsbase,
             .fxsr,
@@ -3249,14 +3321,17 @@ pub const cpu = struct {
             .clwb,
             .clzero,
             .cmov,
+            .crc32,
             .cx16,
             .f16c,
             .fast_15bytenop,
             .fast_bextr,
             .fast_lzcnt,
             .fast_movbe,
+            .fast_scalar_fsqrt,
             .fast_scalar_shift_masks,
             .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
             .fma,
             .fsgsbase,
             .fsrm,
diff --git a/lib/std/zig/fmt.zig b/lib/std/zig/fmt.zig
index 8f59f59c3d..bc9d694b0e 100644
--- a/lib/std/zig/fmt.zig
+++ b/lib/std/zig/fmt.zig
@@ -41,6 +41,7 @@ test "isValidId" {
     try std.testing.expect(!isValidId("a b c"));
     try std.testing.expect(!isValidId("3d"));
     try std.testing.expect(!isValidId("enum"));
+    try std.testing.expect(isValidId("i386"));
 }
 
 /// Print the string as escaped contents of a double quoted or single-quoted string.
diff --git a/lib/std/zig/system/x86.zig b/lib/std/zig/system/x86.zig
index e9d1f0fcbc..1dbdcabfbc 100644
--- a/lib/std/zig/system/x86.zig
+++ b/lib/std/zig/system/x86.zig
@@ -80,11 +80,11 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
     }
     switch (family) {
         3 => {
-            cpu.model = &Target.x86.cpu._i386;
+            cpu.model = &Target.x86.cpu.i386;
             return;
         },
         4 => {
-            cpu.model = &Target.x86.cpu._i486;
+            cpu.model = &Target.x86.cpu.i486;
             return;
         },
         5 => {
@@ -229,7 +229,7 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
     // This is very unscientific, and not necessarily correct.
     switch (family) {
         4 => {
-            cpu.model = &Target.x86.cpu._i486;
+            cpu.model = &Target.x86.cpu.i486;
             return;
         },
         5 => {
author	Andrew Kelley <andrew@ziglang.org>	2022-07-10 03:06:05 -0400
committer	GitHub <noreply@github.com>	2022-07-10 03:06:05 -0400
commit	b88151e0e1553607cbebc197e1111ec4bf53a595 (patch)
tree	cd4f57feae521500fe4eb99a98a798241256d341 /lib/std
parent	3f11d1d56d9747de974b00eab1c880bea7972c01 (diff)
parent	f9bf4889264aee387639bb8a35fdf594236b1283 (diff)
download	zig-b88151e0e1553607cbebc197e1111ec4bf53a595.tar.gz zig-b88151e0e1553607cbebc197e1111ec4bf53a595.zip