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| author | Andrew Kelley <andrew@ziglang.org> | 2022-07-01 21:35:19 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2022-07-01 21:35:19 -0700 |
| commit | d55d98919dd03ac8dcaa787409cacb895dd105d9 (patch) | |
| tree | faa2f6788f648dfe728b131ca6f192bbfefe3ec2 /lib/std/target/powerpc.zig | |
| parent | d19290e603833a197bc8bfc8315561ec77291225 (diff) | |
| download | zig-d55d98919dd03ac8dcaa787409cacb895dd105d9.tar.gz zig-d55d98919dd03ac8dcaa787409cacb895dd105d9.zip | |
update CPU features to LLVM 14
Notable changes:
`_i386`, `_i486`, and `_i686` are renamed to `i386`, `i486`,
and `i686` respectively. `std.zig.fmtId` is enhanced to support
formatting `i386` as `@"i386"`.
Some CPU features which are actually CPU models have been
properly flattened, such as `apple_a12`, `apple_a13`, `apple_a7`,
`cortex_a78c`, `exynos_m4`, `neoverse_e1`, `neoverse_n1`,
`neoverse_n2`, `neoverse_v1`.
Some CPU features have been added and some have been removed, following
LLVM's lead.
CSky CPU features support is added.
Diffstat (limited to 'lib/std/target/powerpc.zig')
| -rw-r--r-- | lib/std/target/powerpc.zig | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/lib/std/target/powerpc.zig b/lib/std/target/powerpc.zig index 3145b2b14c..513a9ad8e0 100644 --- a/lib/std/target/powerpc.zig +++ b/lib/std/target/powerpc.zig @@ -29,14 +29,24 @@ pub const Feature = enum { frsqrte, frsqrtes, fsqrt, + fuse_add_logical, fuse_addi_load, fuse_addis_load, + fuse_arith_add, + fuse_back2back, + fuse_cmp, + fuse_logical, + fuse_logical_add, + fuse_sha3, fuse_store, + fuse_wideimm, + fuse_zeromove, fusion, hard_float, htm, icbt, invariant_function_descriptors, + isa_v206_instructions, isa_v207_instructions, isa_v30_instructions, isa_v31_instructions, @@ -235,6 +245,13 @@ pub const all_features = blk: { .fpu, }), }; + result[@enumToInt(Feature.fuse_add_logical)] = .{ + .llvm_name = "fuse-add-logical", + .description = "Target supports Add with Logical Operations fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; result[@enumToInt(Feature.fuse_addi_load)] = .{ .llvm_name = "fuse-addi-load", .description = "Power8 Addi-Load fusion", @@ -249,6 +266,48 @@ pub const all_features = blk: { .fusion, }), }; + result[@enumToInt(Feature.fuse_arith_add)] = .{ + .llvm_name = "fuse-arith-add", + .description = "Target supports Arithmetic Operations with Add fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fuse_back2back)] = .{ + .llvm_name = "fuse-back2back", + .description = "Target supports general back to back fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fuse_cmp)] = .{ + .llvm_name = "fuse-cmp", + .description = "Target supports Comparison Operations fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fuse_logical)] = .{ + .llvm_name = "fuse-logical", + .description = "Target supports Logical Operations fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fuse_logical_add)] = .{ + .llvm_name = "fuse-logical-add", + .description = "Target supports Logical with Add Operations fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fuse_sha3)] = .{ + .llvm_name = "fuse-sha3", + .description = "Target supports SHA3 assist fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; result[@enumToInt(Feature.fuse_store)] = .{ .llvm_name = "fuse-store", .description = "Target supports store clustering", @@ -256,6 +315,20 @@ pub const all_features = blk: { .fusion, }), }; + result[@enumToInt(Feature.fuse_wideimm)] = .{ + .llvm_name = "fuse-wideimm", + .description = "Target supports Wide-Immediate fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fuse_zeromove)] = .{ + .llvm_name = "fuse-zeromove", + .description = "Target supports move to SPR with branch fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; result[@enumToInt(Feature.fusion)] = .{ .llvm_name = "fusion", .description = "Target supports instruction fusion", @@ -281,6 +354,11 @@ pub const all_features = blk: { .description = "Assume function descriptors are invariant", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.isa_v206_instructions)] = .{ + .llvm_name = "isa-v206-instructions", + .description = "Enable instructions in ISA 2.06.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.isa_v207_instructions)] = .{ .llvm_name = "isa-v207-instructions", .description = "Enable instructions in ISA 2.07.", @@ -707,9 +785,15 @@ pub const cpu = struct { .frsqrte, .frsqrtes, .fsqrt, + .fuse_add_logical, + .fuse_arith_add, + .fuse_logical, + .fuse_logical_add, + .fuse_sha3, .fuse_store, .htm, .icbt, + .isa_v206_instructions, .isel, .ldbrx, .lfiwax, @@ -817,6 +901,7 @@ pub const cpu = struct { .fuse_addis_load, .htm, .icbt, + .isa_v206_instructions, .isa_v207_instructions, .isel, .ldbrx, @@ -851,9 +936,15 @@ pub const cpu = struct { .frsqrte, .frsqrtes, .fsqrt, + .fuse_add_logical, + .fuse_arith_add, + .fuse_logical, + .fuse_logical_add, + .fuse_sha3, .fuse_store, .htm, .icbt, + .isa_v206_instructions, .isel, .ldbrx, .lfiwax, @@ -985,6 +1076,7 @@ pub const cpu = struct { .frsqrte, .frsqrtes, .fsqrt, + .isa_v206_instructions, .isel, .ldbrx, .lfiwax, @@ -1019,6 +1111,7 @@ pub const cpu = struct { .fuse_addis_load, .htm, .icbt, + .isa_v206_instructions, .isa_v207_instructions, .isel, .ldbrx, @@ -1055,6 +1148,7 @@ pub const cpu = struct { .fsqrt, .htm, .icbt, + .isa_v206_instructions, .isel, .ldbrx, .lfiwax, |
