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| author | Andrew Kelley <andrew@ziglang.org> | 2020-01-30 11:31:41 -0500 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2020-01-30 11:31:41 -0500 |
| commit | 70ee818d21c44ec0031b997916694327eb9fc37f (patch) | |
| tree | 6078350717e2a11e25a38208274ff20d66b317f7 /lib/std/target/powerpc.zig | |
| parent | c75f65d38c2c0f5f8f443685a4d694a7ab9c1da3 (diff) | |
| download | zig-70ee818d21c44ec0031b997916694327eb9fc37f.tar.gz zig-70ee818d21c44ec0031b997916694327eb9fc37f.zip | |
update target CPUs and features with llvm10's data
based on zig-llvm-target-details-generator
commit 3aef1b9b4415ed3acfaea4ce8bc233e213548f71
Diffstat (limited to 'lib/std/target/powerpc.zig')
| -rw-r--r-- | lib/std/target/powerpc.zig | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/lib/std/target/powerpc.zig b/lib/std/target/powerpc.zig index 41321f7b04..7681caba81 100644 --- a/lib/std/target/powerpc.zig +++ b/lib/std/target/powerpc.zig @@ -4,6 +4,7 @@ const Cpu = std.Target.Cpu; pub const Feature = enum { @"64bit", @"64bitregs", + allow_unaligned_fp_access, altivec, booke, bpermd, @@ -71,6 +72,11 @@ pub const all_features = blk: { .description = "Enable 64-bit registers usage for ppc32 [beta]", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{ + .llvm_name = "allow-unaligned-fp-access", + .description = "CPU does not trap on unaligned FP access", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.altivec)] = .{ .llvm_name = "altivec", .description = "Enable Altivec instructions", @@ -560,6 +566,7 @@ pub const cpu = struct { .booke, .icbt, .isel, + .spe, }), }; pub const e500mc = Cpu{ @@ -584,6 +591,45 @@ pub const cpu = struct { .stfiwx, }), }; + pub const future = Cpu{ + .name = "future", + .llvm_name = "future", + .features = featureSet(&[_]Feature{ + .@"64bit", + .allow_unaligned_fp_access, + .altivec, + .bpermd, + .cmpb, + .crypto, + .direct_move, + .extdiv, + .fcpsgn, + .fpcvt, + .fprnd, + .fre, + .fres, + .frsqrte, + .frsqrtes, + .fsqrt, + .htm, + .icbt, + .isa_v30_instructions, + .isel, + .ldbrx, + .lfiwax, + .mfocrf, + .partword_atomics, + .popcntd, + .power8_altivec, + .power8_vector, + .power9_altivec, + .power9_vector, + .recipprec, + .stfiwx, + .two_const_nr, + .vsx, + }), + }; pub const g3 = Cpu{ .name = "g3", .llvm_name = "g3", @@ -662,6 +708,7 @@ pub const cpu = struct { .llvm_name = "ppc64le", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -793,6 +840,7 @@ pub const cpu = struct { .llvm_name = "pwr7", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -821,6 +869,7 @@ pub const cpu = struct { .llvm_name = "pwr8", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -856,6 +905,7 @@ pub const cpu = struct { .llvm_name = "pwr9", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -917,6 +967,7 @@ pub const all_cpus = &[_]*const Cpu{ &cpu.e500, &cpu.e500mc, &cpu.e5500, + &cpu.future, &cpu.g3, &cpu.g4, &cpu.@"g4+", |