Merge pull request #20894 from alexrp/target-cleanup-4

`std.Target`: Minor rework to some `isArch()` functions, fix some related issues throughout `std`

1 files changed, 2 insertions, 2 deletions

diff --git a/lib/std/simd.zig b/lib/std/simd.zig
index f5eef1cf97..236b9fbab8 100644
--- a/lib/std/simd.zig
+++ b/lib/std/simd.zig
@@ -18,7 +18,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
             if (std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .avx2 }) and !std.Target.x86.featureSetHas(cpu.features, .prefer_128_bit)) break :blk 256;
             if (std.Target.x86.featureSetHas(cpu.features, .sse)) break :blk 128;
             if (std.Target.x86.featureSetHasAny(cpu.features, .{ .mmx, .@"3dnow" })) break :blk 64;
-        } else if (cpu.arch.isARM()) {
+        } else if (cpu.arch.isArmOrThumb()) {
             if (std.Target.arm.featureSetHas(cpu.features, .neon)) break :blk 128;
         } else if (cpu.arch.isAARCH64()) {
             // SVE allows up to 2048 bits in the specification, as of 2022 the most powerful machine has implemented 512-bit
@@ -26,7 +26,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
             // TODO: Check on this return when bigger values are more common
             if (std.Target.aarch64.featureSetHas(cpu.features, .sve)) break :blk 128;
             if (std.Target.aarch64.featureSetHas(cpu.features, .neon)) break :blk 128;
-        } else if (cpu.arch.isPPC() or cpu.arch.isPPC64()) {
+        } else if (cpu.arch.isPowerPC()) {
             if (std.Target.powerpc.featureSetHas(cpu.features, .altivec)) break :blk 128;
         } else if (cpu.arch.isMIPS()) {
             if (std.Target.mips.featureSetHas(cpu.features, .msa)) break :blk 128;