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| author | Shawn Anastasio <shawn@anastas.io> | 2020-06-03 19:37:14 -0500 |
|---|---|---|
| committer | Shawn Anastasio <shawn@anastas.io> | 2020-07-01 16:10:49 -0500 |
| commit | ec0d775524e0b8b8f0bc41baa3e6d4e11c50557d (patch) | |
| tree | d1ac4e3afacb7d4f03e40f60341dd5b625d25458 /lib/std/os/linux/tls.zig | |
| parent | 7fd937fef4547a98d7c33ea67eca76e6336f9152 (diff) | |
| download | zig-ec0d775524e0b8b8f0bc41baa3e6d4e11c50557d.tar.gz zig-ec0d775524e0b8b8f0bc41baa3e6d4e11c50557d.zip | |
Implement std.os for powerpc64{,le}
Diffstat (limited to 'lib/std/os/linux/tls.zig')
| -rw-r--r-- | lib/std/os/linux/tls.zig | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/lib/std/os/linux/tls.zig b/lib/std/os/linux/tls.zig index 8cba45d4b3..9c79bc3a96 100644 --- a/lib/std/os/linux/tls.zig +++ b/lib/std/os/linux/tls.zig @@ -48,7 +48,7 @@ const TLSVariant = enum { }; const tls_variant = switch (builtin.arch) { - .arm, .armeb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel => TLSVariant.VariantI, + .arm, .armeb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .powerpc, .powerpc64, .powerpc64le => TLSVariant.VariantI, .x86_64, .i386 => TLSVariant.VariantII, else => @compileError("undefined tls_variant for this architecture"), }; @@ -72,12 +72,12 @@ const tls_tp_points_past_tcb = switch (builtin.arch) { // make the generated code more efficient const tls_tp_offset = switch (builtin.arch) { - .mips, .mipsel => 0x7000, + .mips, .mipsel, .powerpc, .powerpc64, .powerpc64le => 0x7000, else => 0, }; const tls_dtv_offset = switch (builtin.arch) { - .mips, .mipsel => 0x8000, + .mips, .mipsel, .powerpc, .powerpc64, .powerpc64le => 0x8000, .riscv32, .riscv64 => 0x800, else => 0, }; @@ -160,6 +160,13 @@ pub fn setThreadPointer(addr: usize) void { const rc = std.os.linux.syscall1(.set_thread_area, addr); assert(rc == 0); }, + .powerpc, .powerpc64, .powerpc64le => { + asm volatile ( + \\ mr 13, %[addr] + : + : [addr] "r" (addr) + ); + }, else => @compileError("Unsupported architecture"), } } |
