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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-10-08 06:29:28 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-08 06:29:28 +0200 |
| commit | 2aea7a42b085f1775889f9d49141faa8098221f9 (patch) | |
| tree | 2d59b52da1298ca39b0b57867144852ae8da18d3 /lib/std/debug/Dwarf.zig | |
| parent | e959a86bb92006eea4d0f15cc1c0f82ecccbc58b (diff) | |
| parent | a54906b46e01f708fb521cb01445808382ef9954 (diff) | |
| download | zig-2aea7a42b085f1775889f9d49141faa8098221f9.tar.gz zig-2aea7a42b085f1775889f9d49141faa8098221f9.zip | |
Merge pull request #25493 from alexrp/std-debug-mips-ppc
`std.debug`: MIPS and PowerPC unwind support + some other stuff
Diffstat (limited to 'lib/std/debug/Dwarf.zig')
| -rw-r--r-- | lib/std/debug/Dwarf.zig | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/lib/std/debug/Dwarf.zig b/lib/std/debug/Dwarf.zig index 0134d10e6b..98d7addb32 100644 --- a/lib/std/debug/Dwarf.zig +++ b/lib/std/debug/Dwarf.zig @@ -1432,8 +1432,10 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 { .aarch64, .aarch64_be => 32, .arm, .armeb, .thumb, .thumbeb => 15, .hexagon => 76, - .loongarch32, .loongarch64 => 32, - .riscv32, .riscv32be, .riscv64, .riscv64be => 32, + .loongarch32, .loongarch64 => 64, + .mips, .mipsel, .mips64, .mips64el => 66, + .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67, + .riscv32, .riscv32be, .riscv64, .riscv64be => 65, .s390x => 65, .x86 => 8, .x86_64 => 16, @@ -1447,6 +1449,8 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 { .arm, .armeb, .thumb, .thumbeb => 11, .hexagon => 30, .loongarch32, .loongarch64 => 22, + .mips, .mipsel, .mips64, .mips64el => 30, + .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1, .riscv32, .riscv32be, .riscv64, .riscv64be => 8, .s390x => 11, .x86 => 5, @@ -1461,6 +1465,8 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 { .arm, .armeb, .thumb, .thumbeb => 13, .hexagon => 29, .loongarch32, .loongarch64 => 3, + .mips, .mipsel, .mips64, .mips64el => 29, + .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1, .riscv32, .riscv32be, .riscv64, .riscv64be => 2, .s390x => 15, .x86 => 4, |