riscv: totally rewrite how we do loads and stores

this commit is a little too large to document fully, however the main gist of it this

- finish the `genInlineMemcpy` implement
- rename `setValue` to `genCopy` as I agree with jacob that it's a better name
- add in `genVarDbgInfo` for a better gdb experience
- follow the x86_64's method for genCall, as the procedure is very similar for us
- add `airSliceLen` as it's trivial
- change up the `airAddWithOverflow implementation a bit
- make sure to not spill of the elem_ty is 0 size
- correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue
and restore them in the epilogue
- add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these,
they make the code very readable and super verbose :)
- fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime.
was happening because we were adding to `max_id` before subtracting from it.

1 files changed, 8 insertions, 8 deletions

diff --git a/lib/std/builtin.zig b/lib/std/builtin.zig
index 15d405eed9..8c57083312 100644
--- a/lib/std/builtin.zig
+++ b/lib/std/builtin.zig
@@ -775,14 +775,14 @@ pub fn default_panic(msg: []const u8, error_return_trace: ?*StackTrace, ret_addr
     }
 
     if (builtin.zig_backend == .stage2_riscv64) {
-        asm volatile ("ecall"
-            :
-            : [number] "{a7}" (64),
-              [arg1] "{a0}" (1),
-              [arg2] "{a1}" (@intFromPtr(msg.ptr)),
-              [arg3] "{a2}" (msg.len),
-            : "rcx", "r11", "memory"
-        );
+        // asm volatile ("ecall"
+        //     :
+        //     : [number] "{a7}" (64),
+        //       [arg1] "{a0}" (1),
+        //       [arg2] "{a1}" (@intFromPtr(msg.ptr)),
+        //       [arg3] "{a2}" (msg.len),
+        //     : "rcx", "r11", "memory"
+        // );
         std.posix.exit(127);
     }