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authorAlex Rønne Petersen <alex@alexrp.com>2025-08-24 21:23:45 +0200
committerAlex Rønne Petersen <alex@alexrp.com>2025-08-25 16:15:17 +0200
commit5d019abe4ec70373db7a75c2a8a3e2d76939817c (patch)
tree4ca5e04afceab7cc8e363d7adfe0436f54a3e82a /lib/std/array_list.zig
parent12686d9b7df8fe4c2663cd8e2136991dc3cf661c (diff)
downloadzig-5d019abe4ec70373db7a75c2a8a3e2d76939817c.tar.gz
zig-5d019abe4ec70373db7a75c2a8a3e2d76939817c.zip
start adding big endian RISC-V support
The big endian RISC-V effort is mostly driven by MIPS (the company) which is pivoting to RISC-V, and presumably needs a big endian variant to fill the niche that big endian MIPS (the ISA) did. GCC already supports these targets, but LLVM support will only appear in 22; this commit just adds the necessary target knowledge and checks on our end.
Diffstat (limited to 'lib/std/array_list.zig')
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