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| author | Andrew Kelley <andrew@ziglang.org> | 2021-08-16 23:30:18 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2021-08-16 23:32:13 -0700 |
| commit | 92b69215e63a3303a5e904ab332e2eec236e0ed2 (patch) | |
| tree | 82dc7298eba67fb6881e0a9014d251073c6a76ae /lib/libunwind/include | |
| parent | 1b8f0d8b56a578dbd699021dd14ea80d743b7cf8 (diff) | |
| download | zig-92b69215e63a3303a5e904ab332e2eec236e0ed2.tar.gz zig-92b69215e63a3303a5e904ab332e2eec236e0ed2.zip | |
update libcxx, libcxxabi, libunwind, and tsan to llvm 13 rc1
Diffstat (limited to 'lib/libunwind/include')
| -rw-r--r-- | lib/libunwind/include/__libunwind_config.h | 17 | ||||
| -rw-r--r-- | lib/libunwind/include/libunwind.h | 47 |
2 files changed, 36 insertions, 28 deletions
diff --git a/lib/libunwind/include/__libunwind_config.h b/lib/libunwind/include/__libunwind_config.h index 34ac6f717d..a50ba05388 100644 --- a/lib/libunwind/include/__libunwind_config.h +++ b/lib/libunwind/include/__libunwind_config.h @@ -131,12 +131,19 @@ #define _LIBUNWIND_CONTEXT_SIZE 16 #define _LIBUNWIND_CURSOR_SIZE 23 # elif defined(__riscv) -# if __riscv_xlen == 64 -# define _LIBUNWIND_TARGET_RISCV 1 -# define _LIBUNWIND_CONTEXT_SIZE 64 -# define _LIBUNWIND_CURSOR_SIZE 76 +# define _LIBUNWIND_TARGET_RISCV 1 +# if defined(__riscv_flen) +# define RISCV_FLEN __riscv_flen # else -# error "Unsupported RISC-V ABI" +# define RISCV_FLEN 0 +# endif +# define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + RISCV_FLEN) / 64) +# if __riscv_xlen == 32 +# define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 7) +# elif __riscv_xlen == 64 +# define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 12) +# else +# error "Unsupported RISC-V ABI" # endif # define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV # elif defined(__ve__) diff --git a/lib/libunwind/include/libunwind.h b/lib/libunwind/include/libunwind.h index 5bae8d02f7..0feecd7bd6 100644 --- a/lib/libunwind/include/libunwind.h +++ b/lib/libunwind/include/libunwind.h @@ -493,16 +493,16 @@ enum { // 64-bit ARM64 registers enum { - UNW_ARM64_X0 = 0, - UNW_ARM64_X1 = 1, - UNW_ARM64_X2 = 2, - UNW_ARM64_X3 = 3, - UNW_ARM64_X4 = 4, - UNW_ARM64_X5 = 5, - UNW_ARM64_X6 = 6, - UNW_ARM64_X7 = 7, - UNW_ARM64_X8 = 8, - UNW_ARM64_X9 = 9, + UNW_ARM64_X0 = 0, + UNW_ARM64_X1 = 1, + UNW_ARM64_X2 = 2, + UNW_ARM64_X3 = 3, + UNW_ARM64_X4 = 4, + UNW_ARM64_X5 = 5, + UNW_ARM64_X6 = 6, + UNW_ARM64_X7 = 7, + UNW_ARM64_X8 = 8, + UNW_ARM64_X9 = 9, UNW_ARM64_X10 = 10, UNW_ARM64_X11 = 11, UNW_ARM64_X12 = 12, @@ -523,24 +523,25 @@ enum { UNW_ARM64_X27 = 27, UNW_ARM64_X28 = 28, UNW_ARM64_X29 = 29, - UNW_ARM64_FP = 29, + UNW_ARM64_FP = 29, UNW_ARM64_X30 = 30, - UNW_ARM64_LR = 30, + UNW_ARM64_LR = 30, UNW_ARM64_X31 = 31, - UNW_ARM64_SP = 31, + UNW_ARM64_SP = 31, + UNW_ARM64_PC = 32, // reserved block UNW_ARM64_RA_SIGN_STATE = 34, // reserved block - UNW_ARM64_D0 = 64, - UNW_ARM64_D1 = 65, - UNW_ARM64_D2 = 66, - UNW_ARM64_D3 = 67, - UNW_ARM64_D4 = 68, - UNW_ARM64_D5 = 69, - UNW_ARM64_D6 = 70, - UNW_ARM64_D7 = 71, - UNW_ARM64_D8 = 72, - UNW_ARM64_D9 = 73, + UNW_ARM64_D0 = 64, + UNW_ARM64_D1 = 65, + UNW_ARM64_D2 = 66, + UNW_ARM64_D3 = 67, + UNW_ARM64_D4 = 68, + UNW_ARM64_D5 = 69, + UNW_ARM64_D6 = 70, + UNW_ARM64_D7 = 71, + UNW_ARM64_D8 = 72, + UNW_ARM64_D9 = 73, UNW_ARM64_D10 = 74, UNW_ARM64_D11 = 75, UNW_ARM64_D12 = 76, |