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| author | Andrew Kelley <andrew@ziglang.org> | 2023-06-24 16:58:19 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-06-24 16:58:19 -0700 |
| commit | 146b79af153bbd5dafda0ba12a040385c7fc58f8 (patch) | |
| tree | 67e3db8b444d65c667e314770fc983a7fc8ba293 /lib/compiler_rt/clear_cache.zig | |
| parent | 13853bef0df3c90633021850cc6d6abaeea03282 (diff) | |
| parent | 21ac0beb436f49fe49c6982a872f2dc48e4bea5e (diff) | |
| download | zig-146b79af153bbd5dafda0ba12a040385c7fc58f8.tar.gz zig-146b79af153bbd5dafda0ba12a040385c7fc58f8.zip | |
Merge pull request #16163 from mlugg/feat/builtins-infer-dest-ty
Infer destination type of cast builtins using result type
Diffstat (limited to 'lib/compiler_rt/clear_cache.zig')
| -rw-r--r-- | lib/compiler_rt/clear_cache.zig | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/compiler_rt/clear_cache.zig b/lib/compiler_rt/clear_cache.zig index e39d726e0f..f2f4fc9bc2 100644 --- a/lib/compiler_rt/clear_cache.zig +++ b/lib/compiler_rt/clear_cache.zig @@ -102,7 +102,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void { // If CTR_EL0.IDC is set, data cache cleaning to the point of unification // is not required for instruction to data coherence. if (((ctr_el0 >> 28) & 0x1) == 0x0) { - const dcache_line_size: usize = @as(usize, 4) << @intCast(u6, (ctr_el0 >> 16) & 15); + const dcache_line_size: usize = @as(usize, 4) << @as(u6, @intCast((ctr_el0 >> 16) & 15)); addr = start & ~(dcache_line_size - 1); while (addr < end) : (addr += dcache_line_size) { asm volatile ("dc cvau, %[addr]" @@ -115,7 +115,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void { // If CTR_EL0.DIC is set, instruction cache invalidation to the point of // unification is not required for instruction to data coherence. if (((ctr_el0 >> 29) & 0x1) == 0x0) { - const icache_line_size: usize = @as(usize, 4) << @intCast(u6, (ctr_el0 >> 0) & 15); + const icache_line_size: usize = @as(usize, 4) << @as(u6, @intCast((ctr_el0 >> 0) & 15)); addr = start & ~(icache_line_size - 1); while (addr < end) : (addr += icache_line_size) { asm volatile ("ic ivau, %[addr]" |