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| author | mparadinha <miguel.p.paradinha@gmail.com> | 2022-01-30 16:02:18 +0000 |
|---|---|---|
| committer | mparadinha <miguel.p.paradinha@gmail.com> | 2022-02-02 08:50:37 +0000 |
| commit | b67b89025cc12785f78a7908e321f8ed0b83afc6 (patch) | |
| tree | 4dc82ae1b3f1d762fb80b4dba1d3c4f1f4a67a1d | |
| parent | cc16ac9314752681300c7e72a4989aeba2ba2579 (diff) | |
| download | zig-b67b89025cc12785f78a7908e321f8ed0b83afc6.tar.gz zig-b67b89025cc12785f78a7908e321f8ed0b83afc6.zip | |
implement store for 8 byte immediates
| -rw-r--r-- | src/arch/x86_64/CodeGen.zig | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index a60a407beb..9356cf49ac 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -1740,6 +1740,24 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type .data = .{ .payload = payload }, }); }, + 8 => { + // TODO: optimization: if the imm is only using the lower + // 4 bytes and can be sign extended we can use a normal mov + // with indirect addressing (mov [reg64], imm32). + + // movabs does not support indirect register addressing + // so we need an extra register and an extra mov. + const tmp_reg = try self.copyToTmpRegister(value_ty, value); + _ = try self.addInst(.{ + .tag = .mov, + .ops = (Mir.Ops{ + .reg1 = reg.to64(), + .reg2 = tmp_reg.to64(), + .flags = 0b10, + }).encode(), + .data = .{ .imm = 0 }, + }); + }, else => { return self.fail("TODO implement set pointee with immediate of ABI size {d}", .{abi_size}); }, |